0001
0002
0003
0004
0005
0006 #include <linux/bitops.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/err.h>
0009 #include <linux/module.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/pm_clock.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/regmap.h>
0014
0015 #include <dt-bindings/clock/qcom,q6sstopcc-qcs404.h>
0016
0017 #include "clk-regmap.h"
0018 #include "clk-branch.h"
0019 #include "common.h"
0020 #include "reset.h"
0021
0022 static struct clk_branch lcc_ahbfabric_cbc_clk = {
0023 .halt_reg = 0x1b004,
0024 .halt_check = BRANCH_HALT,
0025 .clkr = {
0026 .enable_reg = 0x1b004,
0027 .enable_mask = BIT(0),
0028 .hw.init = &(struct clk_init_data){
0029 .name = "lcc_ahbfabric_cbc_clk",
0030 .ops = &clk_branch2_ops,
0031 },
0032 },
0033 };
0034
0035 static struct clk_branch lcc_q6ss_ahbs_cbc_clk = {
0036 .halt_reg = 0x22000,
0037 .halt_check = BRANCH_VOTED,
0038 .clkr = {
0039 .enable_reg = 0x22000,
0040 .enable_mask = BIT(0),
0041 .hw.init = &(struct clk_init_data){
0042 .name = "lcc_q6ss_ahbs_cbc_clk",
0043 .ops = &clk_branch2_ops,
0044 },
0045 },
0046 };
0047
0048 static struct clk_branch lcc_q6ss_tcm_slave_cbc_clk = {
0049 .halt_reg = 0x1c000,
0050 .halt_check = BRANCH_VOTED,
0051 .clkr = {
0052 .enable_reg = 0x1c000,
0053 .enable_mask = BIT(0),
0054 .hw.init = &(struct clk_init_data){
0055 .name = "lcc_q6ss_tcm_slave_cbc_clk",
0056 .ops = &clk_branch2_ops,
0057 },
0058 },
0059 };
0060
0061 static struct clk_branch lcc_q6ss_ahbm_cbc_clk = {
0062 .halt_reg = 0x22004,
0063 .halt_check = BRANCH_VOTED,
0064 .clkr = {
0065 .enable_reg = 0x22004,
0066 .enable_mask = BIT(0),
0067 .hw.init = &(struct clk_init_data){
0068 .name = "lcc_q6ss_ahbm_cbc_clk",
0069 .ops = &clk_branch2_ops,
0070 },
0071 },
0072 };
0073
0074 static struct clk_branch lcc_q6ss_axim_cbc_clk = {
0075 .halt_reg = 0x1c004,
0076 .halt_check = BRANCH_VOTED,
0077 .clkr = {
0078 .enable_reg = 0x1c004,
0079 .enable_mask = BIT(0),
0080 .hw.init = &(struct clk_init_data){
0081 .name = "lcc_q6ss_axim_cbc_clk",
0082 .ops = &clk_branch2_ops,
0083 },
0084 },
0085 };
0086
0087 static struct clk_branch lcc_q6ss_bcr_sleep_clk = {
0088 .halt_reg = 0x6004,
0089 .halt_check = BRANCH_VOTED,
0090 .clkr = {
0091 .enable_reg = 0x6004,
0092 .enable_mask = BIT(0),
0093 .hw.init = &(struct clk_init_data){
0094 .name = "lcc_q6ss_bcr_sleep_clk",
0095 .ops = &clk_branch2_ops,
0096 },
0097 },
0098 };
0099
0100
0101 static struct clk_branch tcsr_lcc_csr_cbcr_clk = {
0102 .halt_reg = 0x8008,
0103 .halt_check = BRANCH_VOTED,
0104 .clkr = {
0105 .enable_reg = 0x8008,
0106 .enable_mask = BIT(0),
0107 .hw.init = &(struct clk_init_data){
0108 .name = "tcsr_lcc_csr_cbcr_clk",
0109 .ops = &clk_branch2_ops,
0110 },
0111 },
0112 };
0113
0114 static struct regmap_config q6sstop_regmap_config = {
0115 .reg_bits = 32,
0116 .reg_stride = 4,
0117 .val_bits = 32,
0118 .fast_io = true,
0119 };
0120
0121 static struct clk_regmap *q6sstop_qcs404_clocks[] = {
0122 [LCC_AHBFABRIC_CBC_CLK] = &lcc_ahbfabric_cbc_clk.clkr,
0123 [LCC_Q6SS_AHBS_CBC_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr,
0124 [LCC_Q6SS_TCM_SLAVE_CBC_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr,
0125 [LCC_Q6SS_AHBM_CBC_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr,
0126 [LCC_Q6SS_AXIM_CBC_CLK] = &lcc_q6ss_axim_cbc_clk.clkr,
0127 [LCC_Q6SS_BCR_SLEEP_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr,
0128 };
0129
0130 static const struct qcom_reset_map q6sstop_qcs404_resets[] = {
0131 [Q6SSTOP_BCR_RESET] = { 0x6000 },
0132 };
0133
0134 static const struct qcom_cc_desc q6sstop_qcs404_desc = {
0135 .config = &q6sstop_regmap_config,
0136 .clks = q6sstop_qcs404_clocks,
0137 .num_clks = ARRAY_SIZE(q6sstop_qcs404_clocks),
0138 .resets = q6sstop_qcs404_resets,
0139 .num_resets = ARRAY_SIZE(q6sstop_qcs404_resets),
0140 };
0141
0142 static struct clk_regmap *tcsr_qcs404_clocks[] = {
0143 [TCSR_Q6SS_LCC_CBCR_CLK] = &tcsr_lcc_csr_cbcr_clk.clkr,
0144 };
0145
0146 static const struct qcom_cc_desc tcsr_qcs404_desc = {
0147 .config = &q6sstop_regmap_config,
0148 .clks = tcsr_qcs404_clocks,
0149 .num_clks = ARRAY_SIZE(tcsr_qcs404_clocks),
0150 };
0151
0152 static const struct of_device_id q6sstopcc_qcs404_match_table[] = {
0153 { .compatible = "qcom,qcs404-q6sstopcc" },
0154 { }
0155 };
0156 MODULE_DEVICE_TABLE(of, q6sstopcc_qcs404_match_table);
0157
0158 static int q6sstopcc_qcs404_probe(struct platform_device *pdev)
0159 {
0160 const struct qcom_cc_desc *desc;
0161 int ret;
0162
0163 ret = devm_pm_runtime_enable(&pdev->dev);
0164 if (ret)
0165 return ret;
0166
0167 ret = devm_pm_clk_create(&pdev->dev);
0168 if (ret)
0169 return ret;
0170
0171 ret = pm_clk_add(&pdev->dev, NULL);
0172 if (ret < 0) {
0173 dev_err(&pdev->dev, "failed to acquire iface clock\n");
0174 return ret;
0175 }
0176
0177 q6sstop_regmap_config.name = "q6sstop_tcsr";
0178 desc = &tcsr_qcs404_desc;
0179
0180 ret = qcom_cc_probe_by_index(pdev, 1, desc);
0181 if (ret)
0182 return ret;
0183
0184 q6sstop_regmap_config.name = "q6sstop_cc";
0185 desc = &q6sstop_qcs404_desc;
0186
0187 ret = qcom_cc_probe_by_index(pdev, 0, desc);
0188 if (ret)
0189 return ret;
0190
0191 return 0;
0192 }
0193
0194 static const struct dev_pm_ops q6sstopcc_pm_ops = {
0195 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
0196 };
0197
0198 static struct platform_driver q6sstopcc_qcs404_driver = {
0199 .probe = q6sstopcc_qcs404_probe,
0200 .driver = {
0201 .name = "qcs404-q6sstopcc",
0202 .of_match_table = q6sstopcc_qcs404_match_table,
0203 .pm = &q6sstopcc_pm_ops,
0204 },
0205 };
0206
0207 module_platform_driver(q6sstopcc_qcs404_driver);
0208
0209 MODULE_DESCRIPTION("QTI QCS404 Q6SSTOP Clock Controller Driver");
0210 MODULE_LICENSE("GPL v2");
