clk/qcom/gpucc-sdm845.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/module.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/regmap.h>
0010
0011 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
0012
0013 #include "common.h"
0014 #include "clk-alpha-pll.h"
0015 #include "clk-branch.h"
0016 #include "clk-pll.h"
0017 #include "clk-rcg.h"
0018 #include "clk-regmap.h"
0019 #include "gdsc.h"
0020
0021 #define CX_GMU_CBCR_SLEEP_MASK      0xf
0022 #define CX_GMU_CBCR_SLEEP_SHIFT     4
0023 #define CX_GMU_CBCR_WAKE_MASK       0xf
0024 #define CX_GMU_CBCR_WAKE_SHIFT      8
0025 #define CLK_DIS_WAIT_SHIFT      12
0026 #define CLK_DIS_WAIT_MASK       (0xf << CLK_DIS_WAIT_SHIFT)
0027
0028 enum {
0029     P_BI_TCXO,
0030     P_GPLL0_OUT_MAIN,
0031     P_GPLL0_OUT_MAIN_DIV,
0032     P_GPU_CC_PLL1_OUT_MAIN,
0033 };
0034
0035 static const struct alpha_pll_config gpu_cc_pll1_config = {
0036     .l = 0x1a,
0037     .alpha = 0xaab,
0038 };
0039
0040 static struct clk_alpha_pll gpu_cc_pll1 = {
0041     .offset = 0x100,
0042     .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
0043     .clkr = {
0044         .hw.init = &(struct clk_init_data){
0045             .name = "gpu_cc_pll1",
0046             .parent_data = &(const struct clk_parent_data){
0047                 .fw_name = "bi_tcxo", .name = "bi_tcxo",
0048             },
0049             .num_parents = 1,
0050             .ops = &clk_alpha_pll_fabia_ops,
0051         },
0052     },
0053 };
0054
0055 static const struct parent_map gpu_cc_parent_map_0[] = {
0056     { P_BI_TCXO, 0 },
0057     { P_GPU_CC_PLL1_OUT_MAIN, 3 },
0058     { P_GPLL0_OUT_MAIN, 5 },
0059     { P_GPLL0_OUT_MAIN_DIV, 6 },
0060 };
0061
0062 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
0063     { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
0064     { .hw = &gpu_cc_pll1.clkr.hw },
0065     { .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
0066     { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
0067 };
0068
0069 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
0070     F(19200000, P_BI_TCXO, 1, 0, 0),
0071     F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
0072     F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
0073     { }
0074 };
0075
0076 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
0077     .cmd_rcgr = 0x1120,
0078     .mnd_width = 0,
0079     .hid_width = 5,
0080     .parent_map = gpu_cc_parent_map_0,
0081     .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
0082     .clkr.hw.init = &(struct clk_init_data){
0083         .name = "gpu_cc_gmu_clk_src",
0084         .parent_data = gpu_cc_parent_data_0,
0085         .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
0086         .ops = &clk_rcg2_shared_ops,
0087     },
0088 };
0089
0090 static struct clk_branch gpu_cc_cx_gmu_clk = {
0091     .halt_reg = 0x1098,
0092     .halt_check = BRANCH_HALT,
0093     .clkr = {
0094         .enable_reg = 0x1098,
0095         .enable_mask = BIT(0),
0096         .hw.init = &(struct clk_init_data){
0097             .name = "gpu_cc_cx_gmu_clk",
0098             .parent_hws = (const struct clk_hw*[]){
0099                 &gpu_cc_gmu_clk_src.clkr.hw,
0100             },
0101             .num_parents = 1,
0102             .flags = CLK_SET_RATE_PARENT,
0103             .ops = &clk_branch2_ops,
0104         },
0105     },
0106 };
0107
0108 static struct clk_branch gpu_cc_cxo_clk = {
0109     .halt_reg = 0x109c,
0110     .halt_check = BRANCH_HALT,
0111     .clkr = {
0112         .enable_reg = 0x109c,
0113         .enable_mask = BIT(0),
0114         .hw.init = &(struct clk_init_data){
0115             .name = "gpu_cc_cxo_clk",
0116             .ops = &clk_branch2_ops,
0117         },
0118     },
0119 };
0120
0121 static struct gdsc gpu_cx_gdsc = {
0122     .gdscr = 0x106c,
0123     .gds_hw_ctrl = 0x1540,
0124     .pd = {
0125         .name = "gpu_cx_gdsc",
0126     },
0127     .pwrsts = PWRSTS_OFF_ON,
0128     .flags = VOTABLE,
0129 };
0130
0131 static struct gdsc gpu_gx_gdsc = {
0132     .gdscr = 0x100c,
0133     .clamp_io_ctrl = 0x1508,
0134     .pd = {
0135         .name = "gpu_gx_gdsc",
0136         .power_on = gdsc_gx_do_nothing_enable,
0137     },
0138     .pwrsts = PWRSTS_OFF_ON,
0139     .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
0140 };
0141
0142 static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
0143     [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
0144     [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
0145     [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
0146     [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
0147 };
0148
0149 static struct gdsc *gpu_cc_sdm845_gdscs[] = {
0150     [GPU_CX_GDSC] = &gpu_cx_gdsc,
0151     [GPU_GX_GDSC] = &gpu_gx_gdsc,
0152 };
0153
0154 static const struct regmap_config gpu_cc_sdm845_regmap_config = {
0155     .reg_bits   = 32,
0156     .reg_stride = 4,
0157     .val_bits   = 32,
0158     .max_register   = 0x8008,
0159     .fast_io    = true,
0160 };
0161
0162 static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
0163     .config = &gpu_cc_sdm845_regmap_config,
0164     .clks = gpu_cc_sdm845_clocks,
0165     .num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
0166     .gdscs = gpu_cc_sdm845_gdscs,
0167     .num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
0168 };
0169
0170 static const struct of_device_id gpu_cc_sdm845_match_table[] = {
0171     { .compatible = "qcom,sdm845-gpucc" },
0172     { }
0173 };
0174 MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
0175
0176 static int gpu_cc_sdm845_probe(struct platform_device *pdev)
0177 {
0178     struct regmap *regmap;
0179     unsigned int value, mask;
0180
0181     regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
0182     if (IS_ERR(regmap))
0183         return PTR_ERR(regmap);
0184
0185     clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
0186
0187     /*
0188      * Configure gpu_cc_cx_gmu_clk with recommended
0189      * wakeup/sleep settings
0190      */
0191     mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
0192     mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
0193     value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
0194     regmap_update_bits(regmap, 0x1098, mask, value);
0195
0196     /* Configure clk_dis_wait for gpu_cx_gdsc */
0197     regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
0198                         8 << CLK_DIS_WAIT_SHIFT);
0199
0200     return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
0201 }
0202
0203 static struct platform_driver gpu_cc_sdm845_driver = {
0204     .probe = gpu_cc_sdm845_probe,
0205     .driver = {
0206         .name = "sdm845-gpucc",
0207         .of_match_table = gpu_cc_sdm845_match_table,
0208     },
0209 };
0210
0211 static int __init gpu_cc_sdm845_init(void)
0212 {
0213     return platform_driver_register(&gpu_cc_sdm845_driver);
0214 }
0215 subsys_initcall(gpu_cc_sdm845_init);
0216
0217 static void __exit gpu_cc_sdm845_exit(void)
0218 {
0219     platform_driver_unregister(&gpu_cc_sdm845_driver);
0220 }
0221 module_exit(gpu_cc_sdm845_exit);
0222
0223 MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
0224 MODULE_LICENSE("GPL v2");