clk/qcom/gdsc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef __QCOM_GDSC_H__
0007 #define __QCOM_GDSC_H__
0008
0009 #include <linux/err.h>
0010 #include <linux/pm_domain.h>
0011
0012 struct regmap;
0013 struct regulator;
0014 struct reset_controller_dev;
0015
0016 /**
0017  * struct gdsc - Globally Distributed Switch Controller
0018  * @pd: generic power domain
0019  * @regmap: regmap for MMIO accesses
0020  * @gdscr: gsdc control register
0021  * @collapse_ctrl: APCS collapse-vote register
0022  * @collapse_mask: APCS collapse-vote mask
0023  * @gds_hw_ctrl: gds_hw_ctrl register
0024  * @cxcs: offsets of branch registers to toggle mem/periph bits in
0025  * @cxc_count: number of @cxcs
0026  * @pwrsts: Possible powerdomain power states
0027  * @en_rest_wait_val: transition delay value for receiving enr ack signal
0028  * @en_few_wait_val: transition delay value for receiving enf ack signal
0029  * @clk_dis_wait_val: transition delay value for halting clock
0030  * @resets: ids of resets associated with this gdsc
0031  * @reset_count: number of @resets
0032  * @rcdev: reset controller
0033  * @dev: the device holding the GDSC, used for pm_runtime calls
0034  */
0035 struct gdsc {
0036     struct generic_pm_domain    pd;
0037     struct generic_pm_domain    *parent;
0038     struct regmap           *regmap;
0039     unsigned int            gdscr;
0040     unsigned int            collapse_ctrl;
0041     unsigned int            collapse_mask;
0042     unsigned int            gds_hw_ctrl;
0043     unsigned int            clamp_io_ctrl;
0044     unsigned int            *cxcs;
0045     unsigned int            cxc_count;
0046     unsigned int            en_rest_wait_val;
0047     unsigned int            en_few_wait_val;
0048     unsigned int            clk_dis_wait_val;
0049     const u8            pwrsts;
0050 /* Powerdomain allowable state bitfields */
0051 #define PWRSTS_OFF      BIT(0)
0052 #define PWRSTS_RET      BIT(1)
0053 #define PWRSTS_ON       BIT(2)
0054 #define PWRSTS_OFF_ON       (PWRSTS_OFF | PWRSTS_ON)
0055 #define PWRSTS_RET_ON       (PWRSTS_RET | PWRSTS_ON)
0056     const u16           flags;
0057 #define VOTABLE     BIT(0)
0058 #define CLAMP_IO    BIT(1)
0059 #define HW_CTRL     BIT(2)
0060 #define SW_RESET    BIT(3)
0061 #define AON_RESET   BIT(4)
0062 #define POLL_CFG_GDSCR  BIT(5)
0063 #define ALWAYS_ON   BIT(6)
0064 #define RETAIN_FF_ENABLE    BIT(7)
0065 #define NO_RET_PERIPH   BIT(8)
0066     struct reset_controller_dev *rcdev;
0067     unsigned int            *resets;
0068     unsigned int            reset_count;
0069
0070     const char          *supply;
0071     struct regulator        *rsupply;
0072     struct device           *dev;
0073 };
0074
0075 struct gdsc_desc {
0076     struct device *dev;
0077     struct gdsc **scs;
0078     size_t num;
0079 };
0080
0081 #ifdef CONFIG_QCOM_GDSC
0082 int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
0083           struct regmap *);
0084 void gdsc_unregister(struct gdsc_desc *desc);
0085 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
0086 #else
0087 static inline int gdsc_register(struct gdsc_desc *desc,
0088                 struct reset_controller_dev *rcdev,
0089                 struct regmap *r)
0090 {
0091     return -ENOSYS;
0092 }
0093
0094 static inline void gdsc_unregister(struct gdsc_desc *desc) {};
0095 #endif /* CONFIG_QCOM_GDSC */
0096 #endif /* __QCOM_GDSC_H__ */