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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/bitops.h>
0007 #include <linux/delay.h>
0008 #include <linux/err.h>
0009 #include <linux/export.h>
0010 #include <linux/jiffies.h>
0011 #include <linux/kernel.h>
0012 #include <linux/ktime.h>
0013 #include <linux/pm_domain.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/reset-controller.h>
0018 #include <linux/slab.h>
0019 #include "gdsc.h"
0020 
0021 #define PWR_ON_MASK     BIT(31)
0022 #define EN_REST_WAIT_MASK   GENMASK_ULL(23, 20)
0023 #define EN_FEW_WAIT_MASK    GENMASK_ULL(19, 16)
0024 #define CLK_DIS_WAIT_MASK   GENMASK_ULL(15, 12)
0025 #define SW_OVERRIDE_MASK    BIT(2)
0026 #define HW_CONTROL_MASK     BIT(1)
0027 #define SW_COLLAPSE_MASK    BIT(0)
0028 #define GMEM_CLAMP_IO_MASK  BIT(0)
0029 #define GMEM_RESET_MASK     BIT(4)
0030 
0031 /* CFG_GDSCR */
0032 #define GDSC_POWER_UP_COMPLETE      BIT(16)
0033 #define GDSC_POWER_DOWN_COMPLETE    BIT(15)
0034 #define GDSC_RETAIN_FF_ENABLE       BIT(11)
0035 #define CFG_GDSCR_OFFSET        0x4
0036 
0037 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
0038 #define EN_REST_WAIT_VAL    0x2
0039 #define EN_FEW_WAIT_VAL     0x8
0040 #define CLK_DIS_WAIT_VAL    0x2
0041 
0042 /* Transition delay shifts */
0043 #define EN_REST_WAIT_SHIFT  20
0044 #define EN_FEW_WAIT_SHIFT   16
0045 #define CLK_DIS_WAIT_SHIFT  12
0046 
0047 #define RETAIN_MEM      BIT(14)
0048 #define RETAIN_PERIPH       BIT(13)
0049 
0050 #define TIMEOUT_US      500
0051 
0052 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
0053 
0054 enum gdsc_status {
0055     GDSC_OFF,
0056     GDSC_ON
0057 };
0058 
0059 static int gdsc_pm_runtime_get(struct gdsc *sc)
0060 {
0061     if (!sc->dev)
0062         return 0;
0063 
0064     return pm_runtime_resume_and_get(sc->dev);
0065 }
0066 
0067 static int gdsc_pm_runtime_put(struct gdsc *sc)
0068 {
0069     if (!sc->dev)
0070         return 0;
0071 
0072     return pm_runtime_put_sync(sc->dev);
0073 }
0074 
0075 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
0076 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
0077 {
0078     unsigned int reg;
0079     u32 val;
0080     int ret;
0081 
0082     if (sc->flags & POLL_CFG_GDSCR)
0083         reg = sc->gdscr + CFG_GDSCR_OFFSET;
0084     else if (sc->gds_hw_ctrl)
0085         reg = sc->gds_hw_ctrl;
0086     else
0087         reg = sc->gdscr;
0088 
0089     ret = regmap_read(sc->regmap, reg, &val);
0090     if (ret)
0091         return ret;
0092 
0093     if (sc->flags & POLL_CFG_GDSCR) {
0094         switch (status) {
0095         case GDSC_ON:
0096             return !!(val & GDSC_POWER_UP_COMPLETE);
0097         case GDSC_OFF:
0098             return !!(val & GDSC_POWER_DOWN_COMPLETE);
0099         }
0100     }
0101 
0102     switch (status) {
0103     case GDSC_ON:
0104         return !!(val & PWR_ON_MASK);
0105     case GDSC_OFF:
0106         return !(val & PWR_ON_MASK);
0107     }
0108 
0109     return -EINVAL;
0110 }
0111 
0112 static int gdsc_hwctrl(struct gdsc *sc, bool en)
0113 {
0114     u32 val = en ? HW_CONTROL_MASK : 0;
0115 
0116     return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
0117 }
0118 
0119 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
0120 {
0121     ktime_t start;
0122 
0123     start = ktime_get();
0124     do {
0125         if (gdsc_check_status(sc, status))
0126             return 0;
0127     } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
0128 
0129     if (gdsc_check_status(sc, status))
0130         return 0;
0131 
0132     return -ETIMEDOUT;
0133 }
0134 
0135 static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
0136 {
0137     u32 reg, mask;
0138     int ret;
0139 
0140     if (sc->collapse_mask) {
0141         reg = sc->collapse_ctrl;
0142         mask = sc->collapse_mask;
0143     } else {
0144         reg = sc->gdscr;
0145         mask = SW_COLLAPSE_MASK;
0146     }
0147 
0148     ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
0149     if (ret)
0150         return ret;
0151 
0152     return 0;
0153 }
0154 
0155 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
0156 {
0157     int ret;
0158 
0159     if (status == GDSC_ON && sc->rsupply) {
0160         ret = regulator_enable(sc->rsupply);
0161         if (ret < 0)
0162             return ret;
0163     }
0164 
0165     ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);
0166 
0167     /* If disabling votable gdscs, don't poll on status */
0168     if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
0169         /*
0170          * Add a short delay here to ensure that an enable
0171          * right after it was disabled does not put it in an
0172          * unknown state
0173          */
0174         udelay(TIMEOUT_US);
0175         return 0;
0176     }
0177 
0178     if (sc->gds_hw_ctrl) {
0179         /*
0180          * The gds hw controller asserts/de-asserts the status bit soon
0181          * after it receives a power on/off request from a master.
0182          * The controller then takes around 8 xo cycles to start its
0183          * internal state machine and update the status bit. During
0184          * this time, the status bit does not reflect the true status
0185          * of the core.
0186          * Add a delay of 1 us between writing to the SW_COLLAPSE bit
0187          * and polling the status bit.
0188          */
0189         udelay(1);
0190     }
0191 
0192     ret = gdsc_poll_status(sc, status);
0193     WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
0194 
0195     if (!ret && status == GDSC_OFF && sc->rsupply) {
0196         ret = regulator_disable(sc->rsupply);
0197         if (ret < 0)
0198             return ret;
0199     }
0200 
0201     return ret;
0202 }
0203 
0204 static inline int gdsc_deassert_reset(struct gdsc *sc)
0205 {
0206     int i;
0207 
0208     for (i = 0; i < sc->reset_count; i++)
0209         sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
0210     return 0;
0211 }
0212 
0213 static inline int gdsc_assert_reset(struct gdsc *sc)
0214 {
0215     int i;
0216 
0217     for (i = 0; i < sc->reset_count; i++)
0218         sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
0219     return 0;
0220 }
0221 
0222 static inline void gdsc_force_mem_on(struct gdsc *sc)
0223 {
0224     int i;
0225     u32 mask = RETAIN_MEM;
0226 
0227     if (!(sc->flags & NO_RET_PERIPH))
0228         mask |= RETAIN_PERIPH;
0229 
0230     for (i = 0; i < sc->cxc_count; i++)
0231         regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
0232 }
0233 
0234 static inline void gdsc_clear_mem_on(struct gdsc *sc)
0235 {
0236     int i;
0237     u32 mask = RETAIN_MEM;
0238 
0239     if (!(sc->flags & NO_RET_PERIPH))
0240         mask |= RETAIN_PERIPH;
0241 
0242     for (i = 0; i < sc->cxc_count; i++)
0243         regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
0244 }
0245 
0246 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
0247 {
0248     regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
0249                GMEM_CLAMP_IO_MASK, 0);
0250 }
0251 
0252 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
0253 {
0254     regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
0255                GMEM_CLAMP_IO_MASK, 1);
0256 }
0257 
0258 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
0259 {
0260     regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
0261                GMEM_RESET_MASK, 1);
0262     udelay(1);
0263     regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
0264                GMEM_RESET_MASK, 0);
0265 }
0266 
0267 static void gdsc_retain_ff_on(struct gdsc *sc)
0268 {
0269     u32 mask = GDSC_RETAIN_FF_ENABLE;
0270 
0271     regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
0272 }
0273 
0274 static int _gdsc_enable(struct gdsc *sc)
0275 {
0276     int ret;
0277 
0278     if (sc->pwrsts == PWRSTS_ON)
0279         return gdsc_deassert_reset(sc);
0280 
0281     if (sc->flags & SW_RESET) {
0282         gdsc_assert_reset(sc);
0283         udelay(1);
0284         gdsc_deassert_reset(sc);
0285     }
0286 
0287     if (sc->flags & CLAMP_IO) {
0288         if (sc->flags & AON_RESET)
0289             gdsc_assert_reset_aon(sc);
0290         gdsc_deassert_clamp_io(sc);
0291     }
0292 
0293     ret = gdsc_toggle_logic(sc, GDSC_ON);
0294     if (ret)
0295         return ret;
0296 
0297     if (sc->pwrsts & PWRSTS_OFF)
0298         gdsc_force_mem_on(sc);
0299 
0300     /*
0301      * If clocks to this power domain were already on, they will take an
0302      * additional 4 clock cycles to re-enable after the power domain is
0303      * enabled. Delay to account for this. A delay is also needed to ensure
0304      * clocks are not enabled within 400ns of enabling power to the
0305      * memories.
0306      */
0307     udelay(1);
0308 
0309     /* Turn on HW trigger mode if supported */
0310     if (sc->flags & HW_CTRL) {
0311         ret = gdsc_hwctrl(sc, true);
0312         if (ret)
0313             return ret;
0314         /*
0315          * Wait for the GDSC to go through a power down and
0316          * up cycle.  In case a firmware ends up polling status
0317          * bits for the gdsc, it might read an 'on' status before
0318          * the GDSC can finish the power cycle.
0319          * We wait 1us before returning to ensure the firmware
0320          * can't immediately poll the status bits.
0321          */
0322         udelay(1);
0323     }
0324 
0325     if (sc->flags & RETAIN_FF_ENABLE)
0326         gdsc_retain_ff_on(sc);
0327 
0328     return 0;
0329 }
0330 
0331 static int gdsc_enable(struct generic_pm_domain *domain)
0332 {
0333     struct gdsc *sc = domain_to_gdsc(domain);
0334     int ret;
0335 
0336     ret = gdsc_pm_runtime_get(sc);
0337     if (ret)
0338         return ret;
0339 
0340     return _gdsc_enable(sc);
0341 }
0342 
0343 static int _gdsc_disable(struct gdsc *sc)
0344 {
0345     int ret;
0346 
0347     if (sc->pwrsts == PWRSTS_ON)
0348         return gdsc_assert_reset(sc);
0349 
0350     /* Turn off HW trigger mode if supported */
0351     if (sc->flags & HW_CTRL) {
0352         ret = gdsc_hwctrl(sc, false);
0353         if (ret < 0)
0354             return ret;
0355         /*
0356          * Wait for the GDSC to go through a power down and
0357          * up cycle.  In case we end up polling status
0358          * bits for the gdsc before the power cycle is completed
0359          * it might read an 'on' status wrongly.
0360          */
0361         udelay(1);
0362 
0363         ret = gdsc_poll_status(sc, GDSC_ON);
0364         if (ret)
0365             return ret;
0366     }
0367 
0368     if (sc->pwrsts & PWRSTS_OFF)
0369         gdsc_clear_mem_on(sc);
0370 
0371     ret = gdsc_toggle_logic(sc, GDSC_OFF);
0372     if (ret)
0373         return ret;
0374 
0375     if (sc->flags & CLAMP_IO)
0376         gdsc_assert_clamp_io(sc);
0377 
0378     return 0;
0379 }
0380 
0381 static int gdsc_disable(struct generic_pm_domain *domain)
0382 {
0383     struct gdsc *sc = domain_to_gdsc(domain);
0384     int ret;
0385 
0386     ret = _gdsc_disable(sc);
0387 
0388     gdsc_pm_runtime_put(sc);
0389 
0390     return ret;
0391 }
0392 
0393 static int gdsc_init(struct gdsc *sc)
0394 {
0395     u32 mask, val;
0396     int on, ret;
0397 
0398     /*
0399      * Disable HW trigger: collapse/restore occur based on registers writes.
0400      * Disable SW override: Use hardware state-machine for sequencing.
0401      * Configure wait time between states.
0402      */
0403     mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
0404            EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
0405 
0406     if (!sc->en_rest_wait_val)
0407         sc->en_rest_wait_val = EN_REST_WAIT_VAL;
0408     if (!sc->en_few_wait_val)
0409         sc->en_few_wait_val = EN_FEW_WAIT_VAL;
0410     if (!sc->clk_dis_wait_val)
0411         sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
0412 
0413     val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
0414         sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
0415         sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
0416 
0417     ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
0418     if (ret)
0419         return ret;
0420 
0421     /* Force gdsc ON if only ON state is supported */
0422     if (sc->pwrsts == PWRSTS_ON) {
0423         ret = gdsc_toggle_logic(sc, GDSC_ON);
0424         if (ret)
0425             return ret;
0426     }
0427 
0428     on = gdsc_check_status(sc, GDSC_ON);
0429     if (on < 0)
0430         return on;
0431 
0432     if (on) {
0433         /* The regulator must be on, sync the kernel state */
0434         if (sc->rsupply) {
0435             ret = regulator_enable(sc->rsupply);
0436             if (ret < 0)
0437                 return ret;
0438         }
0439 
0440         /* ...and the power-domain */
0441         ret = gdsc_pm_runtime_get(sc);
0442         if (ret) {
0443             if (sc->rsupply)
0444                 regulator_disable(sc->rsupply);
0445             return ret;
0446         }
0447 
0448         /*
0449          * Votable GDSCs can be ON due to Vote from other masters.
0450          * If a Votable GDSC is ON, make sure we have a Vote.
0451          */
0452         if (sc->flags & VOTABLE) {
0453             ret = gdsc_update_collapse_bit(sc, false);
0454             if (ret)
0455                 return ret;
0456         }
0457 
0458         /* Turn on HW trigger mode if supported */
0459         if (sc->flags & HW_CTRL) {
0460             ret = gdsc_hwctrl(sc, true);
0461             if (ret < 0)
0462                 return ret;
0463         }
0464 
0465         /*
0466          * Make sure the retain bit is set if the GDSC is already on,
0467          * otherwise we end up turning off the GDSC and destroying all
0468          * the register contents that we thought we were saving.
0469          */
0470         if (sc->flags & RETAIN_FF_ENABLE)
0471             gdsc_retain_ff_on(sc);
0472     } else if (sc->flags & ALWAYS_ON) {
0473         /* If ALWAYS_ON GDSCs are not ON, turn them ON */
0474         gdsc_enable(&sc->pd);
0475         on = true;
0476     }
0477 
0478     if (on || (sc->pwrsts & PWRSTS_RET))
0479         gdsc_force_mem_on(sc);
0480     else
0481         gdsc_clear_mem_on(sc);
0482 
0483     if (sc->flags & ALWAYS_ON)
0484         sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
0485     if (!sc->pd.power_off)
0486         sc->pd.power_off = gdsc_disable;
0487     if (!sc->pd.power_on)
0488         sc->pd.power_on = gdsc_enable;
0489     pm_genpd_init(&sc->pd, NULL, !on);
0490 
0491     return 0;
0492 }
0493 
0494 int gdsc_register(struct gdsc_desc *desc,
0495           struct reset_controller_dev *rcdev, struct regmap *regmap)
0496 {
0497     int i, ret;
0498     struct genpd_onecell_data *data;
0499     struct device *dev = desc->dev;
0500     struct gdsc **scs = desc->scs;
0501     size_t num = desc->num;
0502 
0503     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0504     if (!data)
0505         return -ENOMEM;
0506 
0507     data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
0508                      GFP_KERNEL);
0509     if (!data->domains)
0510         return -ENOMEM;
0511 
0512     for (i = 0; i < num; i++) {
0513         if (!scs[i] || !scs[i]->supply)
0514             continue;
0515 
0516         scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);
0517         if (IS_ERR(scs[i]->rsupply))
0518             return PTR_ERR(scs[i]->rsupply);
0519     }
0520 
0521     data->num_domains = num;
0522     for (i = 0; i < num; i++) {
0523         if (!scs[i])
0524             continue;
0525         if (pm_runtime_enabled(dev))
0526             scs[i]->dev = dev;
0527         scs[i]->regmap = regmap;
0528         scs[i]->rcdev = rcdev;
0529         ret = gdsc_init(scs[i]);
0530         if (ret)
0531             return ret;
0532         data->domains[i] = &scs[i]->pd;
0533     }
0534 
0535     /* Add subdomains */
0536     for (i = 0; i < num; i++) {
0537         if (!scs[i])
0538             continue;
0539         if (scs[i]->parent)
0540             pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
0541         else if (!IS_ERR_OR_NULL(dev->pm_domain))
0542             pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
0543     }
0544 
0545     return of_genpd_add_provider_onecell(dev->of_node, data);
0546 }
0547 
0548 void gdsc_unregister(struct gdsc_desc *desc)
0549 {
0550     int i;
0551     struct device *dev = desc->dev;
0552     struct gdsc **scs = desc->scs;
0553     size_t num = desc->num;
0554 
0555     /* Remove subdomains */
0556     for (i = 0; i < num; i++) {
0557         if (!scs[i])
0558             continue;
0559         if (scs[i]->parent)
0560             pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
0561         else if (!IS_ERR_OR_NULL(dev->pm_domain))
0562             pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
0563     }
0564     of_genpd_del_provider(dev->of_node);
0565 }
0566 
0567 /*
0568  * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
0569  * running in the CX domain so the CPU doesn't need to know anything about the
0570  * GX domain EXCEPT....
0571  *
0572  * Hardware constraints dictate that the GX be powered down before the CX. If
0573  * the GMU crashes it could leave the GX on. In order to successfully bring back
0574  * the device the CPU needs to disable the GX headswitch. There being no sane
0575  * way to reach in and touch that register from deep inside the GPU driver we
0576  * need to set up the infrastructure to be able to ensure that the GPU can
0577  * ensure that the GX is off during this super special case. We do this by
0578  * defining a GX gdsc with a dummy enable function and a "default" disable
0579  * function.
0580  *
0581  * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
0582  * driver. During power up, nothing will happen from the CPU (and the GMU will
0583  * power up normally but during power down this will ensure that the GX domain
0584  * is *really* off - this gives us a semi standard way of doing what we need.
0585  */
0586 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
0587 {
0588     /* Do nothing but give genpd the impression that we were successful */
0589     return 0;
0590 }
0591 EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);
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