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0007 #include <linux/clk-provider.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/regmap.h>
0011
0012 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
0013
0014 #include "common.h"
0015 #include "clk-alpha-pll.h"
0016 #include "clk-branch.h"
0017 #include "clk-pll.h"
0018 #include "clk-rcg.h"
0019 #include "clk-regmap.h"
0020 #include "gdsc.h"
0021 #include "reset.h"
0022
0023 enum {
0024 P_BI_TCXO,
0025 P_CORE_BI_PLL_TEST_SE,
0026 P_GPLL0_OUT_EVEN,
0027 P_GPLL0_OUT_MAIN,
0028 P_GPLL4_OUT_EVEN,
0029 P_GPLL5_OUT_MAIN,
0030 P_SLEEP_CLK,
0031 };
0032
0033 static const struct pll_vco lucid_vco[] = {
0034 { 249600000, 2000000000, 0 },
0035 };
0036
0037 static struct clk_alpha_pll gpll0 = {
0038 .offset = 0x0,
0039 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
0040 .vco_table = lucid_vco,
0041 .num_vco = ARRAY_SIZE(lucid_vco),
0042 .clkr = {
0043 .enable_reg = 0x6d000,
0044 .enable_mask = BIT(0),
0045 .hw.init = &(struct clk_init_data){
0046 .name = "gpll0",
0047 .parent_data = &(const struct clk_parent_data){
0048 .fw_name = "bi_tcxo",
0049 },
0050 .num_parents = 1,
0051 .ops = &clk_alpha_pll_fixed_lucid_ops,
0052 },
0053 },
0054 };
0055
0056 static const struct clk_div_table post_div_table_lucid_even[] = {
0057 { 0x0, 1 },
0058 { 0x1, 2 },
0059 { 0x3, 4 },
0060 { 0x7, 8 },
0061 { }
0062 };
0063
0064 static struct clk_alpha_pll_postdiv gpll0_out_even = {
0065 .offset = 0x0,
0066 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
0067 .post_div_shift = 8,
0068 .post_div_table = post_div_table_lucid_even,
0069 .num_post_div = ARRAY_SIZE(post_div_table_lucid_even),
0070 .width = 4,
0071 .clkr.hw.init = &(struct clk_init_data){
0072 .name = "gpll0_out_even",
0073 .parent_hws = (const struct clk_hw*[]){
0074 &gpll0.clkr.hw,
0075 },
0076 .num_parents = 1,
0077 .ops = &clk_alpha_pll_postdiv_lucid_ops,
0078 },
0079 };
0080
0081 static struct clk_alpha_pll gpll4 = {
0082 .offset = 0x76000,
0083 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
0084 .vco_table = lucid_vco,
0085 .num_vco = ARRAY_SIZE(lucid_vco),
0086 .clkr = {
0087 .enable_reg = 0x6d000,
0088 .enable_mask = BIT(4),
0089 .hw.init = &(struct clk_init_data){
0090 .name = "gpll4",
0091 .parent_data = &(const struct clk_parent_data){
0092 .fw_name = "bi_tcxo",
0093 },
0094 .num_parents = 1,
0095 .ops = &clk_alpha_pll_fixed_lucid_ops,
0096 },
0097 },
0098 };
0099
0100 static struct clk_alpha_pll_postdiv gpll4_out_even = {
0101 .offset = 0x76000,
0102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
0103 .post_div_shift = 8,
0104 .post_div_table = post_div_table_lucid_even,
0105 .num_post_div = ARRAY_SIZE(post_div_table_lucid_even),
0106 .width = 4,
0107 .clkr.hw.init = &(struct clk_init_data){
0108 .name = "gpll4_out_even",
0109 .parent_hws = (const struct clk_hw*[]){
0110 &gpll4.clkr.hw,
0111 },
0112 .num_parents = 1,
0113 .ops = &clk_alpha_pll_postdiv_lucid_ops,
0114 },
0115 };
0116
0117 static struct clk_alpha_pll gpll5 = {
0118 .offset = 0x74000,
0119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
0120 .vco_table = lucid_vco,
0121 .num_vco = ARRAY_SIZE(lucid_vco),
0122 .clkr = {
0123 .enable_reg = 0x6d000,
0124 .enable_mask = BIT(5),
0125 .hw.init = &(struct clk_init_data){
0126 .name = "gpll5",
0127 .parent_data = &(const struct clk_parent_data){
0128 .fw_name = "bi_tcxo",
0129 },
0130 .num_parents = 1,
0131 .ops = &clk_alpha_pll_fixed_lucid_ops,
0132 },
0133 },
0134 };
0135
0136 static const struct parent_map gcc_parent_map_0[] = {
0137 { P_BI_TCXO, 0 },
0138 { P_GPLL0_OUT_MAIN, 1 },
0139 { P_GPLL0_OUT_EVEN, 6 },
0140 { P_CORE_BI_PLL_TEST_SE, 7 },
0141 };
0142
0143 static const struct clk_parent_data gcc_parents_0[] = {
0144 { .fw_name = "bi_tcxo" },
0145 { .hw = &gpll0.clkr.hw },
0146 { .hw = &gpll0_out_even.clkr.hw },
0147 { .fw_name = "core_bi_pll_test_se" },
0148 };
0149
0150 static const struct clk_parent_data gcc_parents_0_ao[] = {
0151 { .fw_name = "bi_tcxo_ao" },
0152 { .hw = &gpll0.clkr.hw },
0153 { .hw = &gpll0_out_even.clkr.hw },
0154 { .fw_name = "core_bi_pll_test_se" },
0155 };
0156
0157 static const struct parent_map gcc_parent_map_2[] = {
0158 { P_BI_TCXO, 0 },
0159 { P_GPLL0_OUT_MAIN, 1 },
0160 { P_GPLL4_OUT_EVEN, 2 },
0161 { P_GPLL5_OUT_MAIN, 5 },
0162 { P_GPLL0_OUT_EVEN, 6 },
0163 { P_CORE_BI_PLL_TEST_SE, 7 },
0164 };
0165
0166 static const struct clk_parent_data gcc_parents_2[] = {
0167 { .fw_name = "bi_tcxo" },
0168 { .hw = &gpll0.clkr.hw },
0169 { .hw = &gpll4_out_even.clkr.hw },
0170 { .hw = &gpll5.clkr.hw },
0171 { .hw = &gpll0_out_even.clkr.hw },
0172 { .fw_name = "core_bi_pll_test_se" },
0173 };
0174
0175 static const struct parent_map gcc_parent_map_3[] = {
0176 { P_BI_TCXO, 0 },
0177 { P_GPLL0_OUT_MAIN, 1 },
0178 { P_SLEEP_CLK, 5 },
0179 { P_GPLL0_OUT_EVEN, 6 },
0180 { P_CORE_BI_PLL_TEST_SE, 7 },
0181 };
0182
0183 static const struct clk_parent_data gcc_parents_3[] = {
0184 { .fw_name = "bi_tcxo" },
0185 { .hw = &gpll0.clkr.hw },
0186 { .fw_name = "sleep_clk", .name = "sleep_clk" },
0187 { .hw = &gpll0_out_even.clkr.hw },
0188 { .fw_name = "core_bi_pll_test_se" },
0189 };
0190
0191 static const struct parent_map gcc_parent_map_4[] = {
0192 { P_BI_TCXO, 0 },
0193 { P_SLEEP_CLK, 5 },
0194 { P_CORE_BI_PLL_TEST_SE, 7 },
0195 };
0196
0197 static const struct clk_parent_data gcc_parents_4[] = {
0198 { .fw_name = "bi_tcxo" },
0199 { .fw_name = "sleep_clk", .name = "sleep_clk" },
0200 { .fw_name = "core_bi_pll_test_se" },
0201 };
0202
0203 static const struct parent_map gcc_parent_map_5[] = {
0204 { P_BI_TCXO, 0 },
0205 { P_GPLL0_OUT_MAIN, 1 },
0206 { P_GPLL4_OUT_EVEN, 2 },
0207 { P_GPLL0_OUT_EVEN, 6 },
0208 { P_CORE_BI_PLL_TEST_SE, 7 },
0209 };
0210
0211 static const struct clk_parent_data gcc_parents_5[] = {
0212 { .fw_name = "bi_tcxo" },
0213 { .hw = &gpll0.clkr.hw },
0214 { .hw = &gpll4_out_even.clkr.hw },
0215 { .hw = &gpll0_out_even.clkr.hw },
0216 { .fw_name = "core_bi_pll_test_se" },
0217 };
0218
0219 static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {
0220 F(9600000, P_BI_TCXO, 2, 0, 0),
0221 F(19200000, P_BI_TCXO, 1, 0, 0),
0222 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
0223 { }
0224 };
0225
0226 static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = {
0227 .cmd_rcgr = 0x11024,
0228 .mnd_width = 8,
0229 .hid_width = 5,
0230 .parent_map = gcc_parent_map_0,
0231 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
0232 .clkr.hw.init = &(struct clk_init_data){
0233 .name = "gcc_blsp1_qup1_i2c_apps_clk_src",
0234 .parent_data = gcc_parents_0,
0235 .num_parents = 4,
0236 .ops = &clk_rcg2_ops,
0237 },
0238 };
0239
0240 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
0241 F(960000, P_BI_TCXO, 10, 1, 2),
0242 F(4800000, P_BI_TCXO, 4, 0, 0),
0243 F(9600000, P_BI_TCXO, 2, 0, 0),
0244 F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4),
0245 F(19200000, P_BI_TCXO, 1, 0, 0),
0246 F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2),
0247 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
0248 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
0249 { }
0250 };
0251
0252 static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
0253 .cmd_rcgr = 0x1100c,
0254 .mnd_width = 8,
0255 .hid_width = 5,
0256 .parent_map = gcc_parent_map_0,
0257 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
0258 .clkr.hw.init = &(struct clk_init_data){
0259 .name = "gcc_blsp1_qup1_spi_apps_clk_src",
0260 .parent_data = gcc_parents_0,
0261 .num_parents = 4,
0262 .ops = &clk_rcg2_ops,
0263 },
0264 };
0265
0266 static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = {
0267 .cmd_rcgr = 0x13024,
0268 .mnd_width = 8,
0269 .hid_width = 5,
0270 .parent_map = gcc_parent_map_0,
0271 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
0272 .clkr.hw.init = &(struct clk_init_data){
0273 .name = "gcc_blsp1_qup2_i2c_apps_clk_src",
0274 .parent_data = gcc_parents_0,
0275 .num_parents = 4,
0276 .ops = &clk_rcg2_ops,
0277 },
0278 };
0279
0280 static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
0281 .cmd_rcgr = 0x1300c,
0282 .mnd_width = 8,
0283 .hid_width = 5,
0284 .parent_map = gcc_parent_map_0,
0285 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
0286 .clkr.hw.init = &(struct clk_init_data){
0287 .name = "gcc_blsp1_qup2_spi_apps_clk_src",
0288 .parent_data = gcc_parents_0,
0289 .num_parents = 4,
0290 .ops = &clk_rcg2_ops,
0291 },
0292 };
0293
0294 static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = {
0295 .cmd_rcgr = 0x15024,
0296 .mnd_width = 8,
0297 .hid_width = 5,
0298 .parent_map = gcc_parent_map_0,
0299 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
0300 .clkr.hw.init = &(struct clk_init_data){
0301 .name = "gcc_blsp1_qup3_i2c_apps_clk_src",
0302 .parent_data = gcc_parents_0,
0303 .num_parents = 4,
0304 .ops = &clk_rcg2_ops,
0305 },
0306 };
0307
0308 static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
0309 .cmd_rcgr = 0x1500c,
0310 .mnd_width = 8,
0311 .hid_width = 5,
0312 .parent_map = gcc_parent_map_0,
0313 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
0314 .clkr.hw.init = &(struct clk_init_data){
0315 .name = "gcc_blsp1_qup3_spi_apps_clk_src",
0316 .parent_data = gcc_parents_0,
0317 .num_parents = 4,
0318 .ops = &clk_rcg2_ops,
0319 },
0320 };
0321
0322 static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = {
0323 .cmd_rcgr = 0x17024,
0324 .mnd_width = 8,
0325 .hid_width = 5,
0326 .parent_map = gcc_parent_map_0,
0327 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
0328 .clkr.hw.init = &(struct clk_init_data){
0329 .name = "gcc_blsp1_qup4_i2c_apps_clk_src",
0330 .parent_data = gcc_parents_0,
0331 .num_parents = 4,
0332 .ops = &clk_rcg2_ops,
0333 },
0334 };
0335
0336 static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = {
0337 .cmd_rcgr = 0x1700c,
0338 .mnd_width = 8,
0339 .hid_width = 5,
0340 .parent_map = gcc_parent_map_0,
0341 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
0342 .clkr.hw.init = &(struct clk_init_data){
0343 .name = "gcc_blsp1_qup4_spi_apps_clk_src",
0344 .parent_data = gcc_parents_0,
0345 .num_parents = 4,
0346 .ops = &clk_rcg2_ops,
0347 },
0348 };
0349
0350 static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
0351 F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625),
0352 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
0353 F(9600000, P_BI_TCXO, 2, 0, 0),
0354 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
0355 F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75),
0356 F(19200000, P_BI_TCXO, 1, 0, 0),
0357 F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2),
0358 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
0359 F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2),
0360 F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2),
0361 F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2),
0362 F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2),
0363 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
0364 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
0365 F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2),
0366 F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2),
0367 F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2),
0368 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
0369 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
0370 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
0371 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
0372 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
0373 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
0374 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
0375 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
0376 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
0377 { }
0378 };
0379
0380 static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
0381 .cmd_rcgr = 0x1200c,
0382 .mnd_width = 16,
0383 .hid_width = 5,
0384 .parent_map = gcc_parent_map_0,
0385 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
0386 .clkr.hw.init = &(struct clk_init_data){
0387 .name = "gcc_blsp1_uart1_apps_clk_src",
0388 .parent_data = gcc_parents_0,
0389 .num_parents = 4,
0390 .ops = &clk_rcg2_ops,
0391 },
0392 };
0393
0394 static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
0395 .cmd_rcgr = 0x1400c,
0396 .mnd_width = 16,
0397 .hid_width = 5,
0398 .parent_map = gcc_parent_map_0,
0399 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
0400 .clkr.hw.init = &(struct clk_init_data){
0401 .name = "gcc_blsp1_uart2_apps_clk_src",
0402 .parent_data = gcc_parents_0,
0403 .num_parents = 4,
0404 .ops = &clk_rcg2_ops,
0405 },
0406 };
0407
0408 static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
0409 .cmd_rcgr = 0x1600c,
0410 .mnd_width = 16,
0411 .hid_width = 5,
0412 .parent_map = gcc_parent_map_0,
0413 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
0414 .clkr.hw.init = &(struct clk_init_data){
0415 .name = "gcc_blsp1_uart3_apps_clk_src",
0416 .parent_data = gcc_parents_0,
0417 .num_parents = 4,
0418 .ops = &clk_rcg2_ops,
0419 },
0420 };
0421
0422 static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = {
0423 .cmd_rcgr = 0x1800c,
0424 .mnd_width = 16,
0425 .hid_width = 5,
0426 .parent_map = gcc_parent_map_0,
0427 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
0428 .clkr.hw.init = &(struct clk_init_data){
0429 .name = "gcc_blsp1_uart4_apps_clk_src",
0430 .parent_data = gcc_parents_0,
0431 .num_parents = 4,
0432 .ops = &clk_rcg2_ops,
0433 },
0434 };
0435
0436 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
0437 F(19200000, P_BI_TCXO, 1, 0, 0),
0438 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
0439 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
0440 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
0441 { }
0442 };
0443
0444 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
0445 .cmd_rcgr = 0x24010,
0446 .mnd_width = 0,
0447 .hid_width = 5,
0448 .parent_map = gcc_parent_map_0,
0449 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
0450 .clkr.hw.init = &(struct clk_init_data){
0451 .name = "gcc_cpuss_ahb_clk_src",
0452 .parent_data = gcc_parents_0_ao,
0453 .num_parents = 4,
0454 .ops = &clk_rcg2_ops,
0455 },
0456 };
0457
0458 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
0459 F(19200000, P_BI_TCXO, 1, 0, 0),
0460 { }
0461 };
0462
0463 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
0464 .cmd_rcgr = 0x2402c,
0465 .mnd_width = 0,
0466 .hid_width = 5,
0467 .parent_map = gcc_parent_map_0,
0468 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
0469 .clkr.hw.init = &(struct clk_init_data){
0470 .name = "gcc_cpuss_rbcpr_clk_src",
0471 .parent_data = gcc_parents_0_ao,
0472 .num_parents = 4,
0473 .ops = &clk_rcg2_ops,
0474 },
0475 };
0476
0477 static const struct freq_tbl ftbl_gcc_emac_clk_src[] = {
0478 F(2500000, P_BI_TCXO, 1, 25, 192),
0479 F(5000000, P_BI_TCXO, 1, 25, 96),
0480 F(19200000, P_BI_TCXO, 1, 0, 0),
0481 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
0482 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
0483 F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0),
0484 { }
0485 };
0486
0487 static struct clk_rcg2 gcc_emac_clk_src = {
0488 .cmd_rcgr = 0x47020,
0489 .mnd_width = 8,
0490 .hid_width = 5,
0491 .parent_map = gcc_parent_map_5,
0492 .freq_tbl = ftbl_gcc_emac_clk_src,
0493 .clkr.hw.init = &(struct clk_init_data){
0494 .name = "gcc_emac_clk_src",
0495 .parent_data = gcc_parents_5,
0496 .num_parents = 5,
0497 .ops = &clk_rcg2_ops,
0498 },
0499 };
0500
0501 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
0502 F(19200000, P_BI_TCXO, 1, 0, 0),
0503 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
0504 F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),
0505 { }
0506 };
0507
0508 static struct clk_rcg2 gcc_emac_ptp_clk_src = {
0509 .cmd_rcgr = 0x47038,
0510 .mnd_width = 0,
0511 .hid_width = 5,
0512 .parent_map = gcc_parent_map_2,
0513 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
0514 .clkr.hw.init = &(struct clk_init_data){
0515 .name = "gcc_emac_ptp_clk_src",
0516 .parent_data = gcc_parents_2,
0517 .num_parents = 6,
0518 .ops = &clk_rcg2_ops,
0519 },
0520 };
0521
0522 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
0523 F(19200000, P_BI_TCXO, 1, 0, 0),
0524 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
0525 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
0526 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
0527 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
0528 { }
0529 };
0530
0531 static struct clk_rcg2 gcc_gp1_clk_src = {
0532 .cmd_rcgr = 0x2b004,
0533 .mnd_width = 8,
0534 .hid_width = 5,
0535 .parent_map = gcc_parent_map_3,
0536 .freq_tbl = ftbl_gcc_gp1_clk_src,
0537 .clkr.hw.init = &(struct clk_init_data){
0538 .name = "gcc_gp1_clk_src",
0539 .parent_data = gcc_parents_3,
0540 .num_parents = 5,
0541 .ops = &clk_rcg2_ops,
0542 },
0543 };
0544
0545 static struct clk_rcg2 gcc_gp2_clk_src = {
0546 .cmd_rcgr = 0x2c004,
0547 .mnd_width = 8,
0548 .hid_width = 5,
0549 .parent_map = gcc_parent_map_3,
0550 .freq_tbl = ftbl_gcc_gp1_clk_src,
0551 .clkr.hw.init = &(struct clk_init_data){
0552 .name = "gcc_gp2_clk_src",
0553 .parent_data = gcc_parents_3,
0554 .num_parents = 5,
0555 .ops = &clk_rcg2_ops,
0556 },
0557 };
0558
0559 static struct clk_rcg2 gcc_gp3_clk_src = {
0560 .cmd_rcgr = 0x2d004,
0561 .mnd_width = 8,
0562 .hid_width = 5,
0563 .parent_map = gcc_parent_map_3,
0564 .freq_tbl = ftbl_gcc_gp1_clk_src,
0565 .clkr.hw.init = &(struct clk_init_data){
0566 .name = "gcc_gp3_clk_src",
0567 .parent_data = gcc_parents_3,
0568 .num_parents = 5,
0569 .ops = &clk_rcg2_ops,
0570 },
0571 };
0572
0573 static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
0574 .cmd_rcgr = 0x37034,
0575 .mnd_width = 16,
0576 .hid_width = 5,
0577 .parent_map = gcc_parent_map_4,
0578 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
0579 .clkr.hw.init = &(struct clk_init_data){
0580 .name = "gcc_pcie_aux_phy_clk_src",
0581 .parent_data = gcc_parents_4,
0582 .num_parents = 3,
0583 .ops = &clk_rcg2_ops,
0584 },
0585 };
0586
0587 static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = {
0588 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
0589 { }
0590 };
0591
0592 static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
0593 .cmd_rcgr = 0x37050,
0594 .mnd_width = 0,
0595 .hid_width = 5,
0596 .parent_map = gcc_parent_map_3,
0597 .freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src,
0598 .clkr.hw.init = &(struct clk_init_data){
0599 .name = "gcc_pcie_rchng_phy_clk_src",
0600 .parent_data = gcc_parents_3,
0601 .num_parents = 5,
0602 .ops = &clk_rcg2_ops,
0603 },
0604 };
0605
0606 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
0607 F(9600000, P_BI_TCXO, 2, 0, 0),
0608 F(19200000, P_BI_TCXO, 1, 0, 0),
0609 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
0610 { }
0611 };
0612
0613 static struct clk_rcg2 gcc_pdm2_clk_src = {
0614 .cmd_rcgr = 0x19010,
0615 .mnd_width = 0,
0616 .hid_width = 5,
0617 .parent_map = gcc_parent_map_0,
0618 .freq_tbl = ftbl_gcc_pdm2_clk_src,
0619 .clkr.hw.init = &(struct clk_init_data){
0620 .name = "gcc_pdm2_clk_src",
0621 .parent_data = gcc_parents_0,
0622 .num_parents = 4,
0623 .ops = &clk_rcg2_ops,
0624 },
0625 };
0626
0627 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
0628 .cmd_rcgr = 0xf00c,
0629 .mnd_width = 8,
0630 .hid_width = 5,
0631 .parent_map = gcc_parent_map_0,
0632 .freq_tbl = ftbl_gcc_gp1_clk_src,
0633 .clkr.hw.init = &(struct clk_init_data){
0634 .name = "gcc_sdcc1_apps_clk_src",
0635 .parent_data = gcc_parents_0,
0636 .num_parents = 4,
0637 .ops = &clk_rcg2_ops,
0638 },
0639 };
0640
0641 static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
0642 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
0643 { }
0644 };
0645
0646 static struct clk_rcg2 gcc_usb30_master_clk_src = {
0647 .cmd_rcgr = 0xb024,
0648 .mnd_width = 8,
0649 .hid_width = 5,
0650 .parent_map = gcc_parent_map_0,
0651 .freq_tbl = ftbl_gcc_usb30_master_clk_src,
0652 .clkr.hw.init = &(struct clk_init_data){
0653 .name = "gcc_usb30_master_clk_src",
0654 .parent_data = gcc_parents_0,
0655 .num_parents = 4,
0656 .ops = &clk_rcg2_ops,
0657 },
0658 };
0659
0660 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
0661 F(19200000, P_BI_TCXO, 1, 0, 0),
0662 { }
0663 };
0664
0665 static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
0666 .cmd_rcgr = 0xb03c,
0667 .mnd_width = 0,
0668 .hid_width = 5,
0669 .parent_map = gcc_parent_map_0,
0670 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
0671 .clkr.hw.init = &(struct clk_init_data){
0672 .name = "gcc_usb30_mock_utmi_clk_src",
0673 .parent_data = gcc_parents_0,
0674 .num_parents = 4,
0675 .ops = &clk_rcg2_ops,
0676 },
0677 };
0678
0679 static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
0680 F(1000000, P_BI_TCXO, 1, 5, 96),
0681 F(19200000, P_BI_TCXO, 1, 0, 0),
0682 { }
0683 };
0684
0685 static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
0686 .cmd_rcgr = 0xb064,
0687 .mnd_width = 16,
0688 .hid_width = 5,
0689 .parent_map = gcc_parent_map_4,
0690 .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
0691 .clkr.hw.init = &(struct clk_init_data){
0692 .name = "gcc_usb3_phy_aux_clk_src",
0693 .parent_data = gcc_parents_4,
0694 .num_parents = 3,
0695 .ops = &clk_rcg2_ops,
0696 },
0697 };
0698
0699 static struct clk_branch gcc_ahb_pcie_link_clk = {
0700 .halt_reg = 0x22004,
0701 .halt_check = BRANCH_HALT,
0702 .clkr = {
0703 .enable_reg = 0x22004,
0704 .enable_mask = BIT(0),
0705 .hw.init = &(struct clk_init_data){
0706 .name = "gcc_ahb_pcie_link_clk",
0707 .ops = &clk_branch2_ops,
0708 },
0709 },
0710 };
0711
0712 static struct clk_branch gcc_blsp1_ahb_clk = {
0713 .halt_reg = 0x10004,
0714 .halt_check = BRANCH_HALT_VOTED,
0715 .clkr = {
0716 .enable_reg = 0x6d008,
0717 .enable_mask = BIT(14),
0718 .hw.init = &(struct clk_init_data){
0719 .name = "gcc_blsp1_ahb_clk",
0720 .ops = &clk_branch2_ops,
0721 },
0722 },
0723 };
0724
0725 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
0726 .halt_reg = 0x11008,
0727 .halt_check = BRANCH_HALT,
0728 .clkr = {
0729 .enable_reg = 0x11008,
0730 .enable_mask = BIT(0),
0731 .hw.init = &(struct clk_init_data){
0732 .name = "gcc_blsp1_qup1_i2c_apps_clk",
0733 .parent_hws = (const struct clk_hw *[]){
0734 &gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw },
0735 .num_parents = 1,
0736 .flags = CLK_SET_RATE_PARENT,
0737 .ops = &clk_branch2_ops,
0738 },
0739 },
0740 };
0741
0742 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
0743 .halt_reg = 0x11004,
0744 .halt_check = BRANCH_HALT,
0745 .clkr = {
0746 .enable_reg = 0x11004,
0747 .enable_mask = BIT(0),
0748 .hw.init = &(struct clk_init_data){
0749 .name = "gcc_blsp1_qup1_spi_apps_clk",
0750 .parent_hws = (const struct clk_hw *[]){
0751 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw },
0752 .num_parents = 1,
0753 .flags = CLK_SET_RATE_PARENT,
0754 .ops = &clk_branch2_ops,
0755 },
0756 },
0757 };
0758
0759 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
0760 .halt_reg = 0x13008,
0761 .halt_check = BRANCH_HALT,
0762 .clkr = {
0763 .enable_reg = 0x13008,
0764 .enable_mask = BIT(0),
0765 .hw.init = &(struct clk_init_data){
0766 .name = "gcc_blsp1_qup2_i2c_apps_clk",
0767 .parent_hws = (const struct clk_hw *[]){
0768 &gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw },
0769 .num_parents = 1,
0770 .flags = CLK_SET_RATE_PARENT,
0771 .ops = &clk_branch2_ops,
0772 },
0773 },
0774 };
0775
0776 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
0777 .halt_reg = 0x13004,
0778 .halt_check = BRANCH_HALT,
0779 .clkr = {
0780 .enable_reg = 0x13004,
0781 .enable_mask = BIT(0),
0782 .hw.init = &(struct clk_init_data){
0783 .name = "gcc_blsp1_qup2_spi_apps_clk",
0784 .parent_hws = (const struct clk_hw *[]){
0785 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw },
0786 .num_parents = 1,
0787 .flags = CLK_SET_RATE_PARENT,
0788 .ops = &clk_branch2_ops,
0789 },
0790 },
0791 };
0792
0793 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
0794 .halt_reg = 0x15008,
0795 .halt_check = BRANCH_HALT,
0796 .clkr = {
0797 .enable_reg = 0x15008,
0798 .enable_mask = BIT(0),
0799 .hw.init = &(struct clk_init_data){
0800 .name = "gcc_blsp1_qup3_i2c_apps_clk",
0801 .parent_hws = (const struct clk_hw *[]){
0802 &gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw },
0803 .num_parents = 1,
0804 .flags = CLK_SET_RATE_PARENT,
0805 .ops = &clk_branch2_ops,
0806 },
0807 },
0808 };
0809
0810 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
0811 .halt_reg = 0x15004,
0812 .halt_check = BRANCH_HALT,
0813 .clkr = {
0814 .enable_reg = 0x15004,
0815 .enable_mask = BIT(0),
0816 .hw.init = &(struct clk_init_data){
0817 .name = "gcc_blsp1_qup3_spi_apps_clk",
0818 .parent_hws = (const struct clk_hw *[]){
0819 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw },
0820 .num_parents = 1,
0821 .flags = CLK_SET_RATE_PARENT,
0822 .ops = &clk_branch2_ops,
0823 },
0824 },
0825 };
0826
0827 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
0828 .halt_reg = 0x17008,
0829 .halt_check = BRANCH_HALT,
0830 .clkr = {
0831 .enable_reg = 0x17008,
0832 .enable_mask = BIT(0),
0833 .hw.init = &(struct clk_init_data){
0834 .name = "gcc_blsp1_qup4_i2c_apps_clk",
0835 .parent_hws = (const struct clk_hw *[]){
0836 &gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw },
0837 .num_parents = 1,
0838 .flags = CLK_SET_RATE_PARENT,
0839 .ops = &clk_branch2_ops,
0840 },
0841 },
0842 };
0843
0844 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
0845 .halt_reg = 0x17004,
0846 .halt_check = BRANCH_HALT,
0847 .clkr = {
0848 .enable_reg = 0x17004,
0849 .enable_mask = BIT(0),
0850 .hw.init = &(struct clk_init_data){
0851 .name = "gcc_blsp1_qup4_spi_apps_clk",
0852 .parent_hws = (const struct clk_hw *[]){
0853 &gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw },
0854 .num_parents = 1,
0855 .flags = CLK_SET_RATE_PARENT,
0856 .ops = &clk_branch2_ops,
0857 },
0858 },
0859 };
0860
0861 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
0862 .halt_reg = 0x12004,
0863 .halt_check = BRANCH_HALT,
0864 .clkr = {
0865 .enable_reg = 0x12004,
0866 .enable_mask = BIT(0),
0867 .hw.init = &(struct clk_init_data){
0868 .name = "gcc_blsp1_uart1_apps_clk",
0869 .parent_hws = (const struct clk_hw *[]){
0870 &gcc_blsp1_uart1_apps_clk_src.clkr.hw },
0871 .num_parents = 1,
0872 .flags = CLK_SET_RATE_PARENT,
0873 .ops = &clk_branch2_ops,
0874 },
0875 },
0876 };
0877
0878 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
0879 .halt_reg = 0x14004,
0880 .halt_check = BRANCH_HALT,
0881 .clkr = {
0882 .enable_reg = 0x14004,
0883 .enable_mask = BIT(0),
0884 .hw.init = &(struct clk_init_data){
0885 .name = "gcc_blsp1_uart2_apps_clk",
0886 .parent_hws = (const struct clk_hw *[]){
0887 &gcc_blsp1_uart2_apps_clk_src.clkr.hw },
0888 .num_parents = 1,
0889 .flags = CLK_SET_RATE_PARENT,
0890 .ops = &clk_branch2_ops,
0891 },
0892 },
0893 };
0894
0895 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
0896 .halt_reg = 0x16004,
0897 .halt_check = BRANCH_HALT,
0898 .clkr = {
0899 .enable_reg = 0x16004,
0900 .enable_mask = BIT(0),
0901 .hw.init = &(struct clk_init_data){
0902 .name = "gcc_blsp1_uart3_apps_clk",
0903 .parent_hws = (const struct clk_hw *[]){
0904 &gcc_blsp1_uart3_apps_clk_src.clkr.hw },
0905 .num_parents = 1,
0906 .flags = CLK_SET_RATE_PARENT,
0907 .ops = &clk_branch2_ops,
0908 },
0909 },
0910 };
0911
0912 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
0913 .halt_reg = 0x18004,
0914 .halt_check = BRANCH_HALT,
0915 .clkr = {
0916 .enable_reg = 0x18004,
0917 .enable_mask = BIT(0),
0918 .hw.init = &(struct clk_init_data){
0919 .name = "gcc_blsp1_uart4_apps_clk",
0920 .parent_hws = (const struct clk_hw *[]){
0921 &gcc_blsp1_uart4_apps_clk_src.clkr.hw },
0922 .num_parents = 1,
0923 .flags = CLK_SET_RATE_PARENT,
0924 .ops = &clk_branch2_ops,
0925 },
0926 },
0927 };
0928
0929 static struct clk_branch gcc_boot_rom_ahb_clk = {
0930 .halt_reg = 0x1c004,
0931 .halt_check = BRANCH_HALT_VOTED,
0932 .hwcg_reg = 0x1c004,
0933 .hwcg_bit = 1,
0934 .clkr = {
0935 .enable_reg = 0x6d008,
0936 .enable_mask = BIT(10),
0937 .hw.init = &(struct clk_init_data){
0938 .name = "gcc_boot_rom_ahb_clk",
0939 .ops = &clk_branch2_ops,
0940 },
0941 },
0942 };
0943
0944 static struct clk_branch gcc_ce1_ahb_clk = {
0945 .halt_reg = 0x2100c,
0946 .halt_check = BRANCH_HALT_VOTED,
0947 .hwcg_reg = 0x2100c,
0948 .hwcg_bit = 1,
0949 .clkr = {
0950 .enable_reg = 0x6d008,
0951 .enable_mask = BIT(3),
0952 .hw.init = &(struct clk_init_data){
0953 .name = "gcc_ce1_ahb_clk",
0954 .ops = &clk_branch2_ops,
0955 },
0956 },
0957 };
0958
0959 static struct clk_branch gcc_ce1_axi_clk = {
0960 .halt_reg = 0x21008,
0961 .halt_check = BRANCH_HALT_VOTED,
0962 .clkr = {
0963 .enable_reg = 0x6d008,
0964 .enable_mask = BIT(4),
0965 .hw.init = &(struct clk_init_data){
0966 .name = "gcc_ce1_axi_clk",
0967 .ops = &clk_branch2_ops,
0968 },
0969 },
0970 };
0971
0972 static struct clk_branch gcc_ce1_clk = {
0973 .halt_reg = 0x21004,
0974 .halt_check = BRANCH_HALT_VOTED,
0975 .clkr = {
0976 .enable_reg = 0x6d008,
0977 .enable_mask = BIT(5),
0978 .hw.init = &(struct clk_init_data){
0979 .name = "gcc_ce1_clk",
0980 .ops = &clk_branch2_ops,
0981 },
0982 },
0983 };
0984
0985 static struct clk_branch gcc_cpuss_rbcpr_clk = {
0986 .halt_reg = 0x24008,
0987 .halt_check = BRANCH_HALT,
0988 .clkr = {
0989 .enable_reg = 0x24008,
0990 .enable_mask = BIT(0),
0991 .hw.init = &(struct clk_init_data){
0992 .name = "gcc_cpuss_rbcpr_clk",
0993 .parent_hws = (const struct clk_hw *[]){
0994 &gcc_cpuss_rbcpr_clk_src.clkr.hw },
0995 .num_parents = 1,
0996 .flags = CLK_SET_RATE_PARENT,
0997 .ops = &clk_branch2_ops,
0998 },
0999 },
1000 };
1001
1002 static struct clk_branch gcc_eth_axi_clk = {
1003 .halt_reg = 0x4701c,
1004 .halt_check = BRANCH_HALT,
1005 .clkr = {
1006 .enable_reg = 0x4701c,
1007 .enable_mask = BIT(0),
1008 .hw.init = &(struct clk_init_data){
1009 .name = "gcc_eth_axi_clk",
1010 .ops = &clk_branch2_ops,
1011 },
1012 },
1013 };
1014
1015 static struct clk_branch gcc_eth_ptp_clk = {
1016 .halt_reg = 0x47018,
1017 .halt_check = BRANCH_HALT,
1018 .clkr = {
1019 .enable_reg = 0x47018,
1020 .enable_mask = BIT(0),
1021 .hw.init = &(struct clk_init_data){
1022 .name = "gcc_eth_ptp_clk",
1023 .parent_hws = (const struct clk_hw *[]){
1024 &gcc_emac_ptp_clk_src.clkr.hw },
1025 .num_parents = 1,
1026 .flags = CLK_SET_RATE_PARENT,
1027 .ops = &clk_branch2_ops,
1028 },
1029 },
1030 };
1031
1032 static struct clk_branch gcc_eth_rgmii_clk = {
1033 .halt_reg = 0x47010,
1034 .halt_check = BRANCH_HALT,
1035 .clkr = {
1036 .enable_reg = 0x47010,
1037 .enable_mask = BIT(0),
1038 .hw.init = &(struct clk_init_data){
1039 .name = "gcc_eth_rgmii_clk",
1040 .parent_hws = (const struct clk_hw *[]){
1041 &gcc_emac_clk_src.clkr.hw },
1042 .num_parents = 1,
1043 .flags = CLK_SET_RATE_PARENT,
1044 .ops = &clk_branch2_ops,
1045 },
1046 },
1047 };
1048
1049 static struct clk_branch gcc_eth_slave_ahb_clk = {
1050 .halt_reg = 0x47014,
1051 .halt_check = BRANCH_HALT,
1052 .clkr = {
1053 .enable_reg = 0x47014,
1054 .enable_mask = BIT(0),
1055 .hw.init = &(struct clk_init_data){
1056 .name = "gcc_eth_slave_ahb_clk",
1057 .ops = &clk_branch2_ops,
1058 },
1059 },
1060 };
1061
1062 static struct clk_branch gcc_gp1_clk = {
1063 .halt_reg = 0x2b000,
1064 .halt_check = BRANCH_HALT,
1065 .clkr = {
1066 .enable_reg = 0x2b000,
1067 .enable_mask = BIT(0),
1068 .hw.init = &(struct clk_init_data){
1069 .name = "gcc_gp1_clk",
1070 .parent_hws = (const struct clk_hw *[]){
1071 &gcc_gp1_clk_src.clkr.hw },
1072 .num_parents = 1,
1073 .flags = CLK_SET_RATE_PARENT,
1074 .ops = &clk_branch2_ops,
1075 },
1076 },
1077 };
1078
1079 static struct clk_branch gcc_gp2_clk = {
1080 .halt_reg = 0x2c000,
1081 .halt_check = BRANCH_HALT,
1082 .clkr = {
1083 .enable_reg = 0x2c000,
1084 .enable_mask = BIT(0),
1085 .hw.init = &(struct clk_init_data){
1086 .name = "gcc_gp2_clk",
1087 .parent_hws = (const struct clk_hw *[]){
1088 &gcc_gp2_clk_src.clkr.hw },
1089 .num_parents = 1,
1090 .flags = CLK_SET_RATE_PARENT,
1091 .ops = &clk_branch2_ops,
1092 },
1093 },
1094 };
1095
1096 static struct clk_branch gcc_gp3_clk = {
1097 .halt_reg = 0x2d000,
1098 .halt_check = BRANCH_HALT,
1099 .clkr = {
1100 .enable_reg = 0x2d000,
1101 .enable_mask = BIT(0),
1102 .hw.init = &(struct clk_init_data){
1103 .name = "gcc_gp3_clk",
1104 .parent_hws = (const struct clk_hw *[]){
1105 &gcc_gp3_clk_src.clkr.hw },
1106 .num_parents = 1,
1107 .flags = CLK_SET_RATE_PARENT,
1108 .ops = &clk_branch2_ops,
1109 },
1110 },
1111 };
1112
1113 static struct clk_branch gcc_pcie_0_clkref_clk = {
1114 .halt_reg = 0x88004,
1115 .halt_check = BRANCH_HALT_DELAY,
1116 .clkr = {
1117 .enable_reg = 0x88004,
1118 .enable_mask = BIT(0),
1119 .hw.init = &(struct clk_init_data){
1120 .name = "gcc_pcie_0_clkref_clk",
1121 .ops = &clk_branch2_ops,
1122 },
1123 },
1124 };
1125
1126 static struct clk_branch gcc_pcie_aux_clk = {
1127 .halt_reg = 0x37024,
1128 .halt_check = BRANCH_HALT_DELAY,
1129 .clkr = {
1130 .enable_reg = 0x6d010,
1131 .enable_mask = BIT(3),
1132 .hw.init = &(struct clk_init_data){
1133 .name = "gcc_pcie_aux_clk",
1134 .ops = &clk_branch2_ops,
1135 },
1136 },
1137 };
1138
1139 static struct clk_branch gcc_pcie_cfg_ahb_clk = {
1140 .halt_reg = 0x3701c,
1141 .halt_check = BRANCH_HALT_VOTED,
1142 .clkr = {
1143 .enable_reg = 0x6d010,
1144 .enable_mask = BIT(2),
1145 .hw.init = &(struct clk_init_data){
1146 .name = "gcc_pcie_cfg_ahb_clk",
1147 .ops = &clk_branch2_ops,
1148 },
1149 },
1150 };
1151
1152 static struct clk_branch gcc_pcie_mstr_axi_clk = {
1153 .halt_reg = 0x37018,
1154 .halt_check = BRANCH_HALT_VOTED,
1155 .clkr = {
1156 .enable_reg = 0x6d010,
1157 .enable_mask = BIT(1),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "gcc_pcie_mstr_axi_clk",
1160 .ops = &clk_branch2_ops,
1161 },
1162 },
1163 };
1164
1165 static struct clk_branch gcc_pcie_pipe_clk = {
1166 .halt_reg = 0x3702c,
1167 .halt_check = BRANCH_HALT_DELAY,
1168 .clkr = {
1169 .enable_reg = 0x6d010,
1170 .enable_mask = BIT(4),
1171 .hw.init = &(struct clk_init_data){
1172 .name = "gcc_pcie_pipe_clk",
1173 .ops = &clk_branch2_ops,
1174 },
1175 },
1176 };
1177
1178 static struct clk_branch gcc_pcie_rchng_phy_clk = {
1179 .halt_reg = 0x37020,
1180 .halt_check = BRANCH_HALT_VOTED,
1181 .clkr = {
1182 .enable_reg = 0x6d010,
1183 .enable_mask = BIT(7),
1184 .hw.init = &(struct clk_init_data){
1185 .name = "gcc_pcie_rchng_phy_clk",
1186 .parent_hws = (const struct clk_hw *[]){
1187 &gcc_pcie_rchng_phy_clk_src.clkr.hw },
1188 .num_parents = 1,
1189 .flags = CLK_SET_RATE_PARENT,
1190 .ops = &clk_branch2_ops,
1191 },
1192 },
1193 };
1194
1195 static struct clk_branch gcc_pcie_sleep_clk = {
1196 .halt_reg = 0x37028,
1197 .halt_check = BRANCH_HALT_VOTED,
1198 .clkr = {
1199 .enable_reg = 0x6d010,
1200 .enable_mask = BIT(6),
1201 .hw.init = &(struct clk_init_data){
1202 .name = "gcc_pcie_sleep_clk",
1203 .parent_hws = (const struct clk_hw *[]){
1204 &gcc_pcie_aux_phy_clk_src.clkr.hw },
1205 .num_parents = 1,
1206 .flags = CLK_SET_RATE_PARENT,
1207 .ops = &clk_branch2_ops,
1208 },
1209 },
1210 };
1211
1212 static struct clk_branch gcc_pcie_slv_axi_clk = {
1213 .halt_reg = 0x37014,
1214 .halt_check = BRANCH_HALT_VOTED,
1215 .hwcg_reg = 0x37014,
1216 .hwcg_bit = 1,
1217 .clkr = {
1218 .enable_reg = 0x6d010,
1219 .enable_mask = BIT(0),
1220 .hw.init = &(struct clk_init_data){
1221 .name = "gcc_pcie_slv_axi_clk",
1222 .ops = &clk_branch2_ops,
1223 },
1224 },
1225 };
1226
1227 static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
1228 .halt_reg = 0x37010,
1229 .halt_check = BRANCH_HALT_VOTED,
1230 .clkr = {
1231 .enable_reg = 0x6d010,
1232 .enable_mask = BIT(5),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "gcc_pcie_slv_q2a_axi_clk",
1235 .ops = &clk_branch2_ops,
1236 },
1237 },
1238 };
1239
1240 static struct clk_branch gcc_pdm2_clk = {
1241 .halt_reg = 0x1900c,
1242 .halt_check = BRANCH_HALT,
1243 .clkr = {
1244 .enable_reg = 0x1900c,
1245 .enable_mask = BIT(0),
1246 .hw.init = &(struct clk_init_data){
1247 .name = "gcc_pdm2_clk",
1248 .parent_hws = (const struct clk_hw *[]){
1249 &gcc_pdm2_clk_src.clkr.hw },
1250 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255 };
1256
1257 static struct clk_branch gcc_pdm_ahb_clk = {
1258 .halt_reg = 0x19004,
1259 .halt_check = BRANCH_HALT,
1260 .hwcg_reg = 0x19004,
1261 .hwcg_bit = 1,
1262 .clkr = {
1263 .enable_reg = 0x19004,
1264 .enable_mask = BIT(0),
1265 .hw.init = &(struct clk_init_data){
1266 .name = "gcc_pdm_ahb_clk",
1267 .ops = &clk_branch2_ops,
1268 },
1269 },
1270 };
1271
1272 static struct clk_branch gcc_pdm_xo4_clk = {
1273 .halt_reg = 0x19008,
1274 .halt_check = BRANCH_HALT,
1275 .clkr = {
1276 .enable_reg = 0x19008,
1277 .enable_mask = BIT(0),
1278 .hw.init = &(struct clk_init_data){
1279 .name = "gcc_pdm_xo4_clk",
1280 .ops = &clk_branch2_ops,
1281 },
1282 },
1283 };
1284
1285 static struct clk_branch gcc_sdcc1_ahb_clk = {
1286 .halt_reg = 0xf008,
1287 .halt_check = BRANCH_HALT,
1288 .clkr = {
1289 .enable_reg = 0xf008,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "gcc_sdcc1_ahb_clk",
1293 .ops = &clk_branch2_ops,
1294 },
1295 },
1296 };
1297
1298 static struct clk_branch gcc_sdcc1_apps_clk = {
1299 .halt_reg = 0xf004,
1300 .halt_check = BRANCH_HALT,
1301 .clkr = {
1302 .enable_reg = 0xf004,
1303 .enable_mask = BIT(0),
1304 .hw.init = &(struct clk_init_data){
1305 .name = "gcc_sdcc1_apps_clk",
1306 .parent_hws = (const struct clk_hw *[]){
1307 &gcc_sdcc1_apps_clk_src.clkr.hw },
1308 .num_parents = 1,
1309 .flags = CLK_SET_RATE_PARENT,
1310 .ops = &clk_branch2_ops,
1311 },
1312 },
1313 };
1314
1315 static struct clk_branch gcc_usb30_master_clk = {
1316 .halt_reg = 0xb010,
1317 .halt_check = BRANCH_HALT,
1318 .clkr = {
1319 .enable_reg = 0xb010,
1320 .enable_mask = BIT(0),
1321 .hw.init = &(struct clk_init_data){
1322 .name = "gcc_usb30_master_clk",
1323 .parent_hws = (const struct clk_hw *[]){
1324 &gcc_usb30_master_clk_src.clkr.hw },
1325 .num_parents = 1,
1326 .flags = CLK_SET_RATE_PARENT,
1327 .ops = &clk_branch2_ops,
1328 },
1329 },
1330 };
1331
1332 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1333 .halt_reg = 0xb020,
1334 .halt_check = BRANCH_HALT,
1335 .clkr = {
1336 .enable_reg = 0xb020,
1337 .enable_mask = BIT(0),
1338 .hw.init = &(struct clk_init_data){
1339 .name = "gcc_usb30_mock_utmi_clk",
1340 .parent_hws = (const struct clk_hw *[]){
1341 &gcc_usb30_mock_utmi_clk_src.clkr.hw },
1342 .num_parents = 1,
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1345 },
1346 },
1347 };
1348
1349 static struct clk_branch gcc_usb30_mstr_axi_clk = {
1350 .halt_reg = 0xb014,
1351 .halt_check = BRANCH_HALT,
1352 .clkr = {
1353 .enable_reg = 0xb014,
1354 .enable_mask = BIT(0),
1355 .hw.init = &(struct clk_init_data){
1356 .name = "gcc_usb30_mstr_axi_clk",
1357 .ops = &clk_branch2_ops,
1358 },
1359 },
1360 };
1361
1362 static struct clk_branch gcc_usb30_sleep_clk = {
1363 .halt_reg = 0xb01c,
1364 .halt_check = BRANCH_HALT,
1365 .clkr = {
1366 .enable_reg = 0xb01c,
1367 .enable_mask = BIT(0),
1368 .hw.init = &(struct clk_init_data){
1369 .name = "gcc_usb30_sleep_clk",
1370 .ops = &clk_branch2_ops,
1371 },
1372 },
1373 };
1374
1375 static struct clk_branch gcc_usb30_slv_ahb_clk = {
1376 .halt_reg = 0xb018,
1377 .halt_check = BRANCH_HALT,
1378 .clkr = {
1379 .enable_reg = 0xb018,
1380 .enable_mask = BIT(0),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "gcc_usb30_slv_ahb_clk",
1383 .ops = &clk_branch2_ops,
1384 },
1385 },
1386 };
1387
1388 static struct clk_branch gcc_usb3_phy_aux_clk = {
1389 .halt_reg = 0xb058,
1390 .halt_check = BRANCH_HALT,
1391 .clkr = {
1392 .enable_reg = 0xb058,
1393 .enable_mask = BIT(0),
1394 .hw.init = &(struct clk_init_data){
1395 .name = "gcc_usb3_phy_aux_clk",
1396 .parent_hws = (const struct clk_hw *[]){
1397 &gcc_usb3_phy_aux_clk_src.clkr.hw },
1398 .num_parents = 1,
1399 .flags = CLK_SET_RATE_PARENT,
1400 .ops = &clk_branch2_ops,
1401 },
1402 },
1403 };
1404
1405 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1406 .halt_reg = 0xb05c,
1407 .halt_check = BRANCH_HALT_DELAY,
1408 .clkr = {
1409 .enable_reg = 0xb05c,
1410 .enable_mask = BIT(0),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "gcc_usb3_phy_pipe_clk",
1413 .ops = &clk_branch2_ops,
1414 },
1415 },
1416 };
1417
1418 static struct clk_branch gcc_usb3_prim_clkref_clk = {
1419 .halt_reg = 0x88000,
1420 .halt_check = BRANCH_HALT_DELAY,
1421 .clkr = {
1422 .enable_reg = 0x88000,
1423 .enable_mask = BIT(0),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "gcc_usb3_prim_clkref_clk",
1426 .ops = &clk_branch2_ops,
1427 },
1428 },
1429 };
1430
1431 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1432 .halt_reg = 0xe004,
1433 .halt_check = BRANCH_HALT,
1434 .hwcg_reg = 0xe004,
1435 .hwcg_bit = 1,
1436 .clkr = {
1437 .enable_reg = 0xe004,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1441 .ops = &clk_branch2_ops,
1442 },
1443 },
1444 };
1445
1446 static struct clk_branch gcc_xo_pcie_link_clk = {
1447 .halt_reg = 0x22008,
1448 .halt_check = BRANCH_HALT,
1449 .clkr = {
1450 .enable_reg = 0x22008,
1451 .enable_mask = BIT(0),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "gcc_xo_pcie_link_clk",
1454 .ops = &clk_branch2_ops,
1455 },
1456 },
1457 };
1458
1459 static struct gdsc usb30_gdsc = {
1460 .gdscr = 0x0b004,
1461 .pd = {
1462 .name = "usb30_gdsc",
1463 },
1464 .pwrsts = PWRSTS_OFF_ON,
1465 };
1466
1467 static struct gdsc pcie_gdsc = {
1468 .gdscr = 0x37004,
1469 .pd = {
1470 .name = "pcie_gdsc",
1471 },
1472 .pwrsts = PWRSTS_OFF_ON,
1473 };
1474
1475 static struct gdsc emac_gdsc = {
1476 .gdscr = 0x47004,
1477 .pd = {
1478 .name = "emac_gdsc",
1479 },
1480 .pwrsts = PWRSTS_OFF_ON,
1481 };
1482
1483 static struct clk_regmap *gcc_sdx55_clocks[] = {
1484 [GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
1485 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1486 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1487 [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] =
1488 &gcc_blsp1_qup1_i2c_apps_clk_src.clkr,
1489 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1490 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] =
1491 &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
1492 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1493 [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] =
1494 &gcc_blsp1_qup2_i2c_apps_clk_src.clkr,
1495 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1496 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] =
1497 &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
1498 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
1499 [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] =
1500 &gcc_blsp1_qup3_i2c_apps_clk_src.clkr,
1501 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
1502 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] =
1503 &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
1504 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
1505 [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] =
1506 &gcc_blsp1_qup4_i2c_apps_clk_src.clkr,
1507 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
1508 [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] =
1509 &gcc_blsp1_qup4_spi_apps_clk_src.clkr,
1510 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1511 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
1512 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1513 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
1514 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
1515 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
1516 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
1517 [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr,
1518 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1519 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
1520 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
1521 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
1522 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
1523 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
1524 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
1525 [GCC_EMAC_CLK_SRC] = &gcc_emac_clk_src.clkr,
1526 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
1527 [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
1528 [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
1529 [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
1530 [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
1531 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1532 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
1533 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1534 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
1535 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1536 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
1537 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
1538 [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
1539 [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
1540 [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
1541 [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
1542 [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
1543 [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
1544 [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
1545 [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
1546 [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
1547 [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
1548 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
1549 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
1550 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
1551 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
1552 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1553 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1554 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
1555 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
1556 [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
1557 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
1558 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
1559 [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
1560 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
1561 [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
1562 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
1563 [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
1564 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
1565 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
1566 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
1567 [GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr,
1568 [GPLL0] = &gpll0.clkr,
1569 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
1570 [GPLL4] = &gpll4.clkr,
1571 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
1572 [GPLL5] = &gpll5.clkr,
1573 };
1574
1575 static const struct qcom_reset_map gcc_sdx55_resets[] = {
1576 [GCC_EMAC_BCR] = { 0x47000 },
1577 [GCC_PCIE_BCR] = { 0x37000 },
1578 [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
1579 [GCC_PCIE_PHY_BCR] = { 0x39000 },
1580 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
1581 [GCC_QUSB2PHY_BCR] = { 0xd000 },
1582 [GCC_USB30_BCR] = { 0xb000 },
1583 [GCC_USB3_PHY_BCR] = { 0xc000 },
1584 [GCC_USB3PHY_PHY_BCR] = { 0xc004 },
1585 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 },
1586 };
1587
1588 static struct gdsc *gcc_sdx55_gdscs[] = {
1589 [USB30_GDSC] = &usb30_gdsc,
1590 [PCIE_GDSC] = &pcie_gdsc,
1591 [EMAC_GDSC] = &emac_gdsc,
1592 };
1593
1594 static const struct regmap_config gcc_sdx55_regmap_config = {
1595 .reg_bits = 32,
1596 .reg_stride = 4,
1597 .val_bits = 32,
1598 .max_register = 0x9b040,
1599 .fast_io = true,
1600 };
1601
1602 static const struct qcom_cc_desc gcc_sdx55_desc = {
1603 .config = &gcc_sdx55_regmap_config,
1604 .clks = gcc_sdx55_clocks,
1605 .num_clks = ARRAY_SIZE(gcc_sdx55_clocks),
1606 .resets = gcc_sdx55_resets,
1607 .num_resets = ARRAY_SIZE(gcc_sdx55_resets),
1608 .gdscs = gcc_sdx55_gdscs,
1609 .num_gdscs = ARRAY_SIZE(gcc_sdx55_gdscs),
1610 };
1611
1612 static const struct of_device_id gcc_sdx55_match_table[] = {
1613 { .compatible = "qcom,gcc-sdx55" },
1614 { }
1615 };
1616 MODULE_DEVICE_TABLE(of, gcc_sdx55_match_table);
1617
1618 static int gcc_sdx55_probe(struct platform_device *pdev)
1619 {
1620 struct regmap *regmap;
1621
1622 regmap = qcom_cc_map(pdev, &gcc_sdx55_desc);
1623 if (IS_ERR(regmap))
1624 return PTR_ERR(regmap);
1625
1626
1627
1628
1629
1630
1631 regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0));
1632 regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
1633 regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
1634
1635 return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap);
1636 }
1637
1638 static struct platform_driver gcc_sdx55_driver = {
1639 .probe = gcc_sdx55_probe,
1640 .driver = {
1641 .name = "gcc-sdx55",
1642 .of_match_table = gcc_sdx55_match_table,
1643 },
1644 };
1645
1646 static int __init gcc_sdx55_init(void)
1647 {
1648 return platform_driver_register(&gcc_sdx55_driver);
1649 }
1650 subsys_initcall(gcc_sdx55_init);
1651
1652 static void __exit gcc_sdx55_exit(void)
1653 {
1654 platform_driver_unregister(&gcc_sdx55_driver);
1655 }
1656 module_exit(gcc_sdx55_exit);
1657
1658 MODULE_DESCRIPTION("QTI GCC SDX55 Driver");
1659 MODULE_LICENSE("GPL v2");
