clk/qcom/clk-spmi-pmic-div.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2017, The Linux Foundation. All rights reserved.
0003  */
0004
0005 #include <linux/bitops.h>
0006 #include <linux/clk.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/delay.h>
0009 #include <linux/err.h>
0010 #include <linux/log2.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015 #include <linux/slab.h>
0016 #include <linux/types.h>
0017
0018 #define REG_DIV_CTL1            0x43
0019 #define DIV_CTL1_DIV_FACTOR_MASK    GENMASK(2, 0)
0020
0021 #define REG_EN_CTL          0x46
0022 #define REG_EN_MASK         BIT(7)
0023
0024 struct clkdiv {
0025     struct regmap       *regmap;
0026     u16         base;
0027     spinlock_t      lock;
0028
0029     struct clk_hw       hw;
0030     unsigned int        cxo_period_ns;
0031 };
0032
0033 static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)
0034 {
0035     return container_of(hw, struct clkdiv, hw);
0036 }
0037
0038 static inline unsigned int div_factor_to_div(unsigned int div_factor)
0039 {
0040     if (!div_factor)
0041         div_factor = 1;
0042
0043     return 1 << (div_factor - 1);
0044 }
0045
0046 static inline unsigned int div_to_div_factor(unsigned int div)
0047 {
0048     return min(ilog2(div) + 1, 7);
0049 }
0050
0051 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)
0052 {
0053     unsigned int val = 0;
0054
0055     regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);
0056
0057     return val & REG_EN_MASK;
0058 }
0059
0060 static int
0061 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,
0062                     unsigned int div_factor)
0063 {
0064     int ret;
0065     unsigned int ns = clkdiv->cxo_period_ns;
0066     unsigned int div = div_factor_to_div(div_factor);
0067
0068     ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
0069                  REG_EN_MASK, enable ? REG_EN_MASK : 0);
0070     if (ret)
0071         return ret;
0072
0073     if (enable)
0074         ndelay((2 + 3 * div) * ns);
0075     else
0076         ndelay(3 * div * ns);
0077
0078     return 0;
0079 }
0080
0081 static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)
0082 {
0083     unsigned int div_factor;
0084
0085     regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
0086     div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
0087
0088     return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
0089 }
0090
0091 static int clk_spmi_pmic_div_enable(struct clk_hw *hw)
0092 {
0093     struct clkdiv *clkdiv = to_clkdiv(hw);
0094     unsigned long flags;
0095     int ret;
0096
0097     spin_lock_irqsave(&clkdiv->lock, flags);
0098     ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
0099     spin_unlock_irqrestore(&clkdiv->lock, flags);
0100
0101     return ret;
0102 }
0103
0104 static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
0105 {
0106     struct clkdiv *clkdiv = to_clkdiv(hw);
0107     unsigned long flags;
0108
0109     spin_lock_irqsave(&clkdiv->lock, flags);
0110     spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
0111     spin_unlock_irqrestore(&clkdiv->lock, flags);
0112 }
0113
0114 static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate,
0115                      unsigned long *parent_rate)
0116 {
0117     unsigned int div, div_factor;
0118
0119     div = DIV_ROUND_UP(*parent_rate, rate);
0120     div_factor = div_to_div_factor(div);
0121     div = div_factor_to_div(div_factor);
0122
0123     return *parent_rate / div;
0124 }
0125
0126 static unsigned long
0127 clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
0128 {
0129     struct clkdiv *clkdiv = to_clkdiv(hw);
0130     unsigned int div_factor;
0131
0132     regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
0133     div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
0134
0135     return parent_rate / div_factor_to_div(div_factor);
0136 }
0137
0138 static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate,
0139                       unsigned long parent_rate)
0140 {
0141     struct clkdiv *clkdiv = to_clkdiv(hw);
0142     unsigned int div_factor = div_to_div_factor(parent_rate / rate);
0143     unsigned long flags;
0144     bool enabled;
0145     int ret;
0146
0147     spin_lock_irqsave(&clkdiv->lock, flags);
0148     enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
0149     if (enabled) {
0150         ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
0151         if (ret)
0152             goto unlock;
0153     }
0154
0155     ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,
0156                  DIV_CTL1_DIV_FACTOR_MASK, div_factor);
0157     if (ret)
0158         goto unlock;
0159
0160     if (enabled)
0161         ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,
0162                               div_factor);
0163
0164 unlock:
0165     spin_unlock_irqrestore(&clkdiv->lock, flags);
0166
0167     return ret;
0168 }
0169
0170 static const struct clk_ops clk_spmi_pmic_div_ops = {
0171     .enable = clk_spmi_pmic_div_enable,
0172     .disable = clk_spmi_pmic_div_disable,
0173     .set_rate = clk_spmi_pmic_div_set_rate,
0174     .recalc_rate = clk_spmi_pmic_div_recalc_rate,
0175     .round_rate = clk_spmi_pmic_div_round_rate,
0176 };
0177
0178 struct spmi_pmic_div_clk_cc {
0179     int     nclks;
0180     struct clkdiv   clks[];
0181 };
0182
0183 static struct clk_hw *
0184 spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data)
0185 {
0186     struct spmi_pmic_div_clk_cc *cc = data;
0187     int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */
0188
0189     if (idx < 0 || idx >= cc->nclks) {
0190         pr_err("%s: index value %u is invalid; allowed range [1, %d]\n",
0191                __func__, clkspec->args[0], cc->nclks);
0192         return ERR_PTR(-EINVAL);
0193     }
0194
0195     return &cc->clks[idx].hw;
0196 }
0197
0198 static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
0199 {
0200     struct spmi_pmic_div_clk_cc *cc;
0201     struct clk_init_data init = {};
0202     struct clkdiv *clkdiv;
0203     struct clk *cxo;
0204     struct regmap *regmap;
0205     struct device *dev = &pdev->dev;
0206     struct device_node *of_node = dev->of_node;
0207     const char *parent_name;
0208     int nclks, i, ret, cxo_hz;
0209     char name[20];
0210     u32 start;
0211
0212     ret = of_property_read_u32(of_node, "reg", &start);
0213     if (ret < 0) {
0214         dev_err(dev, "reg property reading failed\n");
0215         return ret;
0216     }
0217
0218     regmap = dev_get_regmap(dev->parent, NULL);
0219     if (!regmap) {
0220         dev_err(dev, "Couldn't get parent's regmap\n");
0221         return -EINVAL;
0222     }
0223
0224     ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks);
0225     if (ret < 0) {
0226         dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n",
0227             ret);
0228         return ret;
0229     }
0230
0231     if (!nclks)
0232         return -EINVAL;
0233
0234     cc = devm_kzalloc(dev, struct_size(cc, clks, nclks), GFP_KERNEL);
0235     if (!cc)
0236         return -ENOMEM;
0237     cc->nclks = nclks;
0238
0239     cxo = clk_get(dev, "xo");
0240     if (IS_ERR(cxo)) {
0241         ret = PTR_ERR(cxo);
0242         if (ret != -EPROBE_DEFER)
0243             dev_err(dev, "failed to get xo clock\n");
0244         return ret;
0245     }
0246     cxo_hz = clk_get_rate(cxo);
0247     clk_put(cxo);
0248
0249     parent_name = of_clk_get_parent_name(of_node, 0);
0250     if (!parent_name) {
0251         dev_err(dev, "missing parent clock\n");
0252         return -ENODEV;
0253     }
0254
0255     init.name = name;
0256     init.parent_names = &parent_name;
0257     init.num_parents = 1;
0258     init.ops = &clk_spmi_pmic_div_ops;
0259
0260     for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
0261         snprintf(name, sizeof(name), "div_clk%d", i + 1);
0262
0263         spin_lock_init(&clkdiv[i].lock);
0264         clkdiv[i].base = start + i * 0x100;
0265         clkdiv[i].regmap = regmap;
0266         clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;
0267         clkdiv[i].hw.init = &init;
0268
0269         ret = devm_clk_hw_register(dev, &clkdiv[i].hw);
0270         if (ret)
0271             return ret;
0272     }
0273
0274     return devm_of_clk_add_hw_provider(dev, spmi_pmic_div_clk_hw_get, cc);
0275 }
0276
0277 static const struct of_device_id spmi_pmic_clkdiv_match_table[] = {
0278     { .compatible = "qcom,spmi-clkdiv" },
0279     { /* sentinel */ }
0280 };
0281 MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table);
0282
0283 static struct platform_driver spmi_pmic_clkdiv_driver = {
0284     .driver     = {
0285         .name   = "qcom,spmi-pmic-clkdiv",
0286         .of_match_table = spmi_pmic_clkdiv_match_table,
0287     },
0288     .probe      = spmi_pmic_clkdiv_probe,
0289 };
0290 module_platform_driver(spmi_pmic_clkdiv_driver);
0291
0292 MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver");
0293 MODULE_LICENSE("GPL v2");