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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016, Linaro Limited
0004  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
0005  */
0006 
0007 #include <linux/clk-provider.h>
0008 #include <linux/err.h>
0009 #include <linux/export.h>
0010 #include <linux/init.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/mutex.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/soc/qcom/smd-rpm.h>
0018 
0019 #include <dt-bindings/clock/qcom,rpmcc.h>
0020 
0021 #define QCOM_RPM_KEY_SOFTWARE_ENABLE            0x6e657773
0022 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
0023 #define QCOM_RPM_SMD_KEY_RATE               0x007a484b
0024 #define QCOM_RPM_SMD_KEY_ENABLE             0x62616e45
0025 #define QCOM_RPM_SMD_KEY_STATE              0x54415453
0026 #define QCOM_RPM_SCALING_ENABLE_ID          0x2
0027 
0028 #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id,  \
0029                  key)                         \
0030     static struct clk_smd_rpm _platform##_##_active;              \
0031     static struct clk_smd_rpm _platform##_##_name = {             \
0032         .rpm_res_type = (type),                       \
0033         .rpm_clk_id = (r_id),                         \
0034         .rpm_status_id = (stat_id),                   \
0035         .rpm_key = (key),                         \
0036         .peer = &_platform##_##_active,                   \
0037         .rate = INT_MAX,                          \
0038         .hw.init = &(struct clk_init_data){               \
0039             .ops = &clk_smd_rpm_ops,                  \
0040             .name = #_name,                       \
0041             .parent_data =  &(const struct clk_parent_data){ \
0042                     .fw_name = "xo",        \
0043                     .name = "xo_board",     \
0044             },                      \
0045             .num_parents = 1,                     \
0046         },                                \
0047     };                                    \
0048     static struct clk_smd_rpm _platform##_##_active = {           \
0049         .rpm_res_type = (type),                       \
0050         .rpm_clk_id = (r_id),                         \
0051         .rpm_status_id = (stat_id),                   \
0052         .active_only = true,                          \
0053         .rpm_key = (key),                         \
0054         .peer = &_platform##_##_name,                     \
0055         .rate = INT_MAX,                          \
0056         .hw.init = &(struct clk_init_data){               \
0057             .ops = &clk_smd_rpm_ops,                  \
0058             .name = #_active,                     \
0059             .parent_data =  &(const struct clk_parent_data){ \
0060                     .fw_name = "xo",        \
0061                     .name = "xo_board",     \
0062             },                      \
0063             .num_parents = 1,                     \
0064         },                                \
0065     }
0066 
0067 #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id,    \
0068                     stat_id, r, key)                  \
0069     static struct clk_smd_rpm _platform##_##_active;              \
0070     static struct clk_smd_rpm _platform##_##_name = {             \
0071         .rpm_res_type = (type),                       \
0072         .rpm_clk_id = (r_id),                         \
0073         .rpm_status_id = (stat_id),                   \
0074         .rpm_key = (key),                         \
0075         .branch = true,                           \
0076         .peer = &_platform##_##_active,                   \
0077         .rate = (r),                              \
0078         .hw.init = &(struct clk_init_data){               \
0079             .ops = &clk_smd_rpm_branch_ops,               \
0080             .name = #_name,                       \
0081             .parent_data =  &(const struct clk_parent_data){ \
0082                     .fw_name = "xo",        \
0083                     .name = "xo_board",     \
0084             },                      \
0085             .num_parents = 1,                     \
0086         },                                \
0087     };                                    \
0088     static struct clk_smd_rpm _platform##_##_active = {           \
0089         .rpm_res_type = (type),                       \
0090         .rpm_clk_id = (r_id),                         \
0091         .rpm_status_id = (stat_id),                   \
0092         .active_only = true,                          \
0093         .rpm_key = (key),                         \
0094         .branch = true,                           \
0095         .peer = &_platform##_##_name,                     \
0096         .rate = (r),                              \
0097         .hw.init = &(struct clk_init_data){               \
0098             .ops = &clk_smd_rpm_branch_ops,               \
0099             .name = #_active,                     \
0100             .parent_data =  &(const struct clk_parent_data){ \
0101                     .fw_name = "xo",        \
0102                     .name = "xo_board",     \
0103             },                      \
0104             .num_parents = 1,                     \
0105         },                                \
0106     }
0107 
0108 #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id)         \
0109         __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
0110         0, QCOM_RPM_SMD_KEY_RATE)
0111 
0112 #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r)   \
0113         __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type,  \
0114         r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
0115 
0116 #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id)        \
0117         __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
0118         0, QCOM_RPM_SMD_KEY_STATE)
0119 
0120 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r)      \
0121         __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
0122         QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r,               \
0123         QCOM_RPM_KEY_SOFTWARE_ENABLE)
0124 
0125 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active,       \
0126                          r_id, r)                 \
0127         __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
0128         QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r,               \
0129         QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
0130 
0131 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
0132 
0133 struct clk_smd_rpm {
0134     const int rpm_res_type;
0135     const int rpm_key;
0136     const int rpm_clk_id;
0137     const int rpm_status_id;
0138     const bool active_only;
0139     bool enabled;
0140     bool branch;
0141     struct clk_smd_rpm *peer;
0142     struct clk_hw hw;
0143     unsigned long rate;
0144     struct qcom_smd_rpm *rpm;
0145 };
0146 
0147 struct clk_smd_rpm_req {
0148     __le32 key;
0149     __le32 nbytes;
0150     __le32 value;
0151 };
0152 
0153 struct rpm_smd_clk_desc {
0154     struct clk_smd_rpm **clks;
0155     size_t num_clks;
0156 };
0157 
0158 static DEFINE_MUTEX(rpm_smd_clk_lock);
0159 
0160 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
0161 {
0162     int ret;
0163     struct clk_smd_rpm_req req = {
0164         .key = cpu_to_le32(r->rpm_key),
0165         .nbytes = cpu_to_le32(sizeof(u32)),
0166         .value = cpu_to_le32(r->branch ? 1 : INT_MAX),
0167     };
0168 
0169     ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
0170                  r->rpm_res_type, r->rpm_clk_id, &req,
0171                  sizeof(req));
0172     if (ret)
0173         return ret;
0174     ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
0175                  r->rpm_res_type, r->rpm_clk_id, &req,
0176                  sizeof(req));
0177     if (ret)
0178         return ret;
0179 
0180     return 0;
0181 }
0182 
0183 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
0184                        unsigned long rate)
0185 {
0186     struct clk_smd_rpm_req req = {
0187         .key = cpu_to_le32(r->rpm_key),
0188         .nbytes = cpu_to_le32(sizeof(u32)),
0189         .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
0190     };
0191 
0192     return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
0193                   r->rpm_res_type, r->rpm_clk_id, &req,
0194                   sizeof(req));
0195 }
0196 
0197 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
0198                       unsigned long rate)
0199 {
0200     struct clk_smd_rpm_req req = {
0201         .key = cpu_to_le32(r->rpm_key),
0202         .nbytes = cpu_to_le32(sizeof(u32)),
0203         .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
0204     };
0205 
0206     return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
0207                   r->rpm_res_type, r->rpm_clk_id, &req,
0208                   sizeof(req));
0209 }
0210 
0211 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
0212                 unsigned long *active, unsigned long *sleep)
0213 {
0214     *active = rate;
0215 
0216     /*
0217      * Active-only clocks don't care what the rate is during sleep. So,
0218      * they vote for zero.
0219      */
0220     if (r->active_only)
0221         *sleep = 0;
0222     else
0223         *sleep = *active;
0224 }
0225 
0226 static int clk_smd_rpm_prepare(struct clk_hw *hw)
0227 {
0228     struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
0229     struct clk_smd_rpm *peer = r->peer;
0230     unsigned long this_rate = 0, this_sleep_rate = 0;
0231     unsigned long peer_rate = 0, peer_sleep_rate = 0;
0232     unsigned long active_rate, sleep_rate;
0233     int ret = 0;
0234 
0235     mutex_lock(&rpm_smd_clk_lock);
0236 
0237     /* Don't send requests to the RPM if the rate has not been set. */
0238     if (!r->rate)
0239         goto out;
0240 
0241     to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
0242 
0243     /* Take peer clock's rate into account only if it's enabled. */
0244     if (peer->enabled)
0245         to_active_sleep(peer, peer->rate,
0246                 &peer_rate, &peer_sleep_rate);
0247 
0248     active_rate = max(this_rate, peer_rate);
0249 
0250     if (r->branch)
0251         active_rate = !!active_rate;
0252 
0253     ret = clk_smd_rpm_set_rate_active(r, active_rate);
0254     if (ret)
0255         goto out;
0256 
0257     sleep_rate = max(this_sleep_rate, peer_sleep_rate);
0258     if (r->branch)
0259         sleep_rate = !!sleep_rate;
0260 
0261     ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
0262     if (ret)
0263         /* Undo the active set vote and restore it */
0264         ret = clk_smd_rpm_set_rate_active(r, peer_rate);
0265 
0266 out:
0267     if (!ret)
0268         r->enabled = true;
0269 
0270     mutex_unlock(&rpm_smd_clk_lock);
0271 
0272     return ret;
0273 }
0274 
0275 static void clk_smd_rpm_unprepare(struct clk_hw *hw)
0276 {
0277     struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
0278     struct clk_smd_rpm *peer = r->peer;
0279     unsigned long peer_rate = 0, peer_sleep_rate = 0;
0280     unsigned long active_rate, sleep_rate;
0281     int ret;
0282 
0283     mutex_lock(&rpm_smd_clk_lock);
0284 
0285     if (!r->rate)
0286         goto out;
0287 
0288     /* Take peer clock's rate into account only if it's enabled. */
0289     if (peer->enabled)
0290         to_active_sleep(peer, peer->rate, &peer_rate,
0291                 &peer_sleep_rate);
0292 
0293     active_rate = r->branch ? !!peer_rate : peer_rate;
0294     ret = clk_smd_rpm_set_rate_active(r, active_rate);
0295     if (ret)
0296         goto out;
0297 
0298     sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
0299     ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
0300     if (ret)
0301         goto out;
0302 
0303     r->enabled = false;
0304 
0305 out:
0306     mutex_unlock(&rpm_smd_clk_lock);
0307 }
0308 
0309 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
0310                 unsigned long parent_rate)
0311 {
0312     struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
0313     struct clk_smd_rpm *peer = r->peer;
0314     unsigned long active_rate, sleep_rate;
0315     unsigned long this_rate = 0, this_sleep_rate = 0;
0316     unsigned long peer_rate = 0, peer_sleep_rate = 0;
0317     int ret = 0;
0318 
0319     mutex_lock(&rpm_smd_clk_lock);
0320 
0321     if (!r->enabled)
0322         goto out;
0323 
0324     to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
0325 
0326     /* Take peer clock's rate into account only if it's enabled. */
0327     if (peer->enabled)
0328         to_active_sleep(peer, peer->rate,
0329                 &peer_rate, &peer_sleep_rate);
0330 
0331     active_rate = max(this_rate, peer_rate);
0332     ret = clk_smd_rpm_set_rate_active(r, active_rate);
0333     if (ret)
0334         goto out;
0335 
0336     sleep_rate = max(this_sleep_rate, peer_sleep_rate);
0337     ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
0338     if (ret)
0339         goto out;
0340 
0341     r->rate = rate;
0342 
0343 out:
0344     mutex_unlock(&rpm_smd_clk_lock);
0345 
0346     return ret;
0347 }
0348 
0349 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
0350                    unsigned long *parent_rate)
0351 {
0352     /*
0353      * RPM handles rate rounding and we don't have a way to
0354      * know what the rate will be, so just return whatever
0355      * rate is requested.
0356      */
0357     return rate;
0358 }
0359 
0360 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
0361                          unsigned long parent_rate)
0362 {
0363     struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
0364 
0365     /*
0366      * RPM handles rate rounding and we don't have a way to
0367      * know what the rate will be, so just return whatever
0368      * rate was set.
0369      */
0370     return r->rate;
0371 }
0372 
0373 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
0374 {
0375     int ret;
0376     struct clk_smd_rpm_req req = {
0377         .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
0378         .nbytes = cpu_to_le32(sizeof(u32)),
0379         .value = cpu_to_le32(1),
0380     };
0381 
0382     ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
0383                  QCOM_SMD_RPM_MISC_CLK,
0384                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
0385     if (ret) {
0386         pr_err("RPM clock scaling (sleep set) not enabled!\n");
0387         return ret;
0388     }
0389 
0390     ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
0391                  QCOM_SMD_RPM_MISC_CLK,
0392                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
0393     if (ret) {
0394         pr_err("RPM clock scaling (active set) not enabled!\n");
0395         return ret;
0396     }
0397 
0398     pr_debug("%s: RPM clock scaling is enabled\n", __func__);
0399     return 0;
0400 }
0401 
0402 static const struct clk_ops clk_smd_rpm_ops = {
0403     .prepare    = clk_smd_rpm_prepare,
0404     .unprepare  = clk_smd_rpm_unprepare,
0405     .set_rate   = clk_smd_rpm_set_rate,
0406     .round_rate = clk_smd_rpm_round_rate,
0407     .recalc_rate    = clk_smd_rpm_recalc_rate,
0408 };
0409 
0410 static const struct clk_ops clk_smd_rpm_branch_ops = {
0411     .prepare    = clk_smd_rpm_prepare,
0412     .unprepare  = clk_smd_rpm_unprepare,
0413     .recalc_rate    = clk_smd_rpm_recalc_rate,
0414 };
0415 
0416 DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
0417 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
0418 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
0419 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
0420 DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
0421 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000);
0422 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000);
0423 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4, 19200000);
0424 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5, 19200000);
0425 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1, 19200000);
0426 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 19200000);
0427 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000);
0428 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000);
0429 
0430 static struct clk_smd_rpm *msm8916_clks[] = {
0431     [RPM_SMD_PCNOC_CLK]     = &msm8916_pcnoc_clk,
0432     [RPM_SMD_PCNOC_A_CLK]       = &msm8916_pcnoc_a_clk,
0433     [RPM_SMD_SNOC_CLK]      = &msm8916_snoc_clk,
0434     [RPM_SMD_SNOC_A_CLK]        = &msm8916_snoc_a_clk,
0435     [RPM_SMD_BIMC_CLK]      = &msm8916_bimc_clk,
0436     [RPM_SMD_BIMC_A_CLK]        = &msm8916_bimc_a_clk,
0437     [RPM_SMD_QDSS_CLK]      = &msm8916_qdss_clk,
0438     [RPM_SMD_QDSS_A_CLK]        = &msm8916_qdss_a_clk,
0439     [RPM_SMD_BB_CLK1]       = &msm8916_bb_clk1,
0440     [RPM_SMD_BB_CLK1_A]     = &msm8916_bb_clk1_a,
0441     [RPM_SMD_BB_CLK2]       = &msm8916_bb_clk2,
0442     [RPM_SMD_BB_CLK2_A]     = &msm8916_bb_clk2_a,
0443     [RPM_SMD_RF_CLK1]       = &msm8916_rf_clk1,
0444     [RPM_SMD_RF_CLK1_A]     = &msm8916_rf_clk1_a,
0445     [RPM_SMD_RF_CLK2]       = &msm8916_rf_clk2,
0446     [RPM_SMD_RF_CLK2_A]     = &msm8916_rf_clk2_a,
0447     [RPM_SMD_BB_CLK1_PIN]       = &msm8916_bb_clk1_pin,
0448     [RPM_SMD_BB_CLK1_A_PIN]     = &msm8916_bb_clk1_a_pin,
0449     [RPM_SMD_BB_CLK2_PIN]       = &msm8916_bb_clk2_pin,
0450     [RPM_SMD_BB_CLK2_A_PIN]     = &msm8916_bb_clk2_a_pin,
0451     [RPM_SMD_RF_CLK1_PIN]       = &msm8916_rf_clk1_pin,
0452     [RPM_SMD_RF_CLK1_A_PIN]     = &msm8916_rf_clk1_a_pin,
0453     [RPM_SMD_RF_CLK2_PIN]       = &msm8916_rf_clk2_pin,
0454     [RPM_SMD_RF_CLK2_A_PIN]     = &msm8916_rf_clk2_a_pin,
0455 };
0456 
0457 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
0458     .clks = msm8916_clks,
0459     .num_clks = ARRAY_SIZE(msm8916_clks),
0460 };
0461 
0462 DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
0463 
0464 static struct clk_smd_rpm *msm8936_clks[] = {
0465     [RPM_SMD_PCNOC_CLK]     = &msm8916_pcnoc_clk,
0466     [RPM_SMD_PCNOC_A_CLK]       = &msm8916_pcnoc_a_clk,
0467     [RPM_SMD_SNOC_CLK]      = &msm8916_snoc_clk,
0468     [RPM_SMD_SNOC_A_CLK]        = &msm8916_snoc_a_clk,
0469     [RPM_SMD_BIMC_CLK]      = &msm8916_bimc_clk,
0470     [RPM_SMD_BIMC_A_CLK]        = &msm8916_bimc_a_clk,
0471     [RPM_SMD_SYSMMNOC_CLK]      = &msm8936_sysmmnoc_clk,
0472     [RPM_SMD_SYSMMNOC_A_CLK]    = &msm8936_sysmmnoc_a_clk,
0473     [RPM_SMD_QDSS_CLK]      = &msm8916_qdss_clk,
0474     [RPM_SMD_QDSS_A_CLK]        = &msm8916_qdss_a_clk,
0475     [RPM_SMD_BB_CLK1]       = &msm8916_bb_clk1,
0476     [RPM_SMD_BB_CLK1_A]     = &msm8916_bb_clk1_a,
0477     [RPM_SMD_BB_CLK2]       = &msm8916_bb_clk2,
0478     [RPM_SMD_BB_CLK2_A]     = &msm8916_bb_clk2_a,
0479     [RPM_SMD_RF_CLK1]       = &msm8916_rf_clk1,
0480     [RPM_SMD_RF_CLK1_A]     = &msm8916_rf_clk1_a,
0481     [RPM_SMD_RF_CLK2]       = &msm8916_rf_clk2,
0482     [RPM_SMD_RF_CLK2_A]     = &msm8916_rf_clk2_a,
0483     [RPM_SMD_BB_CLK1_PIN]       = &msm8916_bb_clk1_pin,
0484     [RPM_SMD_BB_CLK1_A_PIN]     = &msm8916_bb_clk1_a_pin,
0485     [RPM_SMD_BB_CLK2_PIN]       = &msm8916_bb_clk2_pin,
0486     [RPM_SMD_BB_CLK2_A_PIN]     = &msm8916_bb_clk2_a_pin,
0487     [RPM_SMD_RF_CLK1_PIN]       = &msm8916_rf_clk1_pin,
0488     [RPM_SMD_RF_CLK1_A_PIN]     = &msm8916_rf_clk1_a_pin,
0489     [RPM_SMD_RF_CLK2_PIN]       = &msm8916_rf_clk2_pin,
0490     [RPM_SMD_RF_CLK2_A_PIN]     = &msm8916_rf_clk2_a_pin,
0491 };
0492 
0493 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
0494         .clks = msm8936_clks,
0495         .num_clks = ARRAY_SIZE(msm8936_clks),
0496 };
0497 
0498 DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
0499 DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
0500 DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
0501 DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
0502 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1, 19200000);
0503 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2, 19200000);
0504 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4, 19200000);
0505 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5, 19200000);
0506 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6, 19200000);
0507 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000);
0508 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000);
0509 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000);
0510 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1, 19200000);
0511 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2, 19200000);
0512 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4, 19200000);
0513 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5, 19200000);
0514 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6, 19200000);
0515 
0516 static struct clk_smd_rpm *msm8974_clks[] = {
0517     [RPM_SMD_PNOC_CLK]      = &msm8916_pcnoc_clk,
0518     [RPM_SMD_PNOC_A_CLK]        = &msm8916_pcnoc_a_clk,
0519     [RPM_SMD_SNOC_CLK]      = &msm8916_snoc_clk,
0520     [RPM_SMD_SNOC_A_CLK]        = &msm8916_snoc_a_clk,
0521     [RPM_SMD_CNOC_CLK]      = &msm8974_cnoc_clk,
0522     [RPM_SMD_CNOC_A_CLK]        = &msm8974_cnoc_a_clk,
0523     [RPM_SMD_MMSSNOC_AHB_CLK]   = &msm8974_mmssnoc_ahb_clk,
0524     [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
0525     [RPM_SMD_BIMC_CLK]      = &msm8916_bimc_clk,
0526     [RPM_SMD_GFX3D_CLK_SRC]     = &msm8974_gfx3d_clk_src,
0527     [RPM_SMD_GFX3D_A_CLK_SRC]   = &msm8974_gfx3d_a_clk_src,
0528     [RPM_SMD_BIMC_A_CLK]        = &msm8916_bimc_a_clk,
0529     [RPM_SMD_OCMEMGX_CLK]       = &msm8974_ocmemgx_clk,
0530     [RPM_SMD_OCMEMGX_A_CLK]     = &msm8974_ocmemgx_a_clk,
0531     [RPM_SMD_QDSS_CLK]      = &msm8916_qdss_clk,
0532     [RPM_SMD_QDSS_A_CLK]        = &msm8916_qdss_a_clk,
0533     [RPM_SMD_CXO_D0]        = &msm8974_cxo_d0,
0534     [RPM_SMD_CXO_D0_A]      = &msm8974_cxo_d0_a,
0535     [RPM_SMD_CXO_D1]        = &msm8974_cxo_d1,
0536     [RPM_SMD_CXO_D1_A]      = &msm8974_cxo_d1_a,
0537     [RPM_SMD_CXO_A0]        = &msm8974_cxo_a0,
0538     [RPM_SMD_CXO_A0_A]      = &msm8974_cxo_a0_a,
0539     [RPM_SMD_CXO_A1]        = &msm8974_cxo_a1,
0540     [RPM_SMD_CXO_A1_A]      = &msm8974_cxo_a1_a,
0541     [RPM_SMD_CXO_A2]        = &msm8974_cxo_a2,
0542     [RPM_SMD_CXO_A2_A]      = &msm8974_cxo_a2_a,
0543     [RPM_SMD_DIFF_CLK]      = &msm8974_diff_clk,
0544     [RPM_SMD_DIFF_A_CLK]        = &msm8974_diff_a_clk,
0545     [RPM_SMD_DIV_CLK1]      = &msm8974_div_clk1,
0546     [RPM_SMD_DIV_A_CLK1]        = &msm8974_div_a_clk1,
0547     [RPM_SMD_DIV_CLK2]      = &msm8974_div_clk2,
0548     [RPM_SMD_DIV_A_CLK2]        = &msm8974_div_a_clk2,
0549     [RPM_SMD_CXO_D0_PIN]        = &msm8974_cxo_d0_pin,
0550     [RPM_SMD_CXO_D0_A_PIN]      = &msm8974_cxo_d0_a_pin,
0551     [RPM_SMD_CXO_D1_PIN]        = &msm8974_cxo_d1_pin,
0552     [RPM_SMD_CXO_D1_A_PIN]      = &msm8974_cxo_d1_a_pin,
0553     [RPM_SMD_CXO_A0_PIN]        = &msm8974_cxo_a0_pin,
0554     [RPM_SMD_CXO_A0_A_PIN]      = &msm8974_cxo_a0_a_pin,
0555     [RPM_SMD_CXO_A1_PIN]        = &msm8974_cxo_a1_pin,
0556     [RPM_SMD_CXO_A1_A_PIN]      = &msm8974_cxo_a1_a_pin,
0557     [RPM_SMD_CXO_A2_PIN]        = &msm8974_cxo_a2_pin,
0558     [RPM_SMD_CXO_A2_A_PIN]      = &msm8974_cxo_a2_a_pin,
0559 };
0560 
0561 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
0562     .clks = msm8974_clks,
0563     .num_clks = ARRAY_SIZE(msm8974_clks),
0564 };
0565 
0566 DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
0567 
0568 static struct clk_smd_rpm *msm8976_clks[] = {
0569     [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
0570     [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
0571     [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
0572     [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
0573     [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
0574     [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
0575     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
0576     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
0577     [RPM_SMD_SYSMMNOC_CLK]  = &msm8936_sysmmnoc_clk,
0578     [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk,
0579     [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
0580     [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
0581     [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
0582     [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
0583     [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
0584     [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
0585     [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
0586     [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
0587     [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
0588     [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
0589     [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
0590     [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
0591     [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
0592     [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
0593     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
0594     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
0595 };
0596 
0597 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
0598     .clks = msm8976_clks,
0599     .num_clks = ARRAY_SIZE(msm8976_clks),
0600 };
0601 
0602 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000);
0603 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000);
0604 
0605 DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
0606 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
0607 
0608 DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk,
0609               QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
0610 static struct clk_smd_rpm *msm8992_clks[] = {
0611     [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
0612     [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
0613     [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
0614     [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
0615     [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
0616     [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
0617     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
0618     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
0619     [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
0620     [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
0621     [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
0622     [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
0623     [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
0624     [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
0625     [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
0626     [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
0627     [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
0628     [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
0629     [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
0630     [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
0631     [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
0632     [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
0633     [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
0634     [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
0635     [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
0636     [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
0637     [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
0638     [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
0639     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
0640     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
0641     [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
0642     [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
0643     [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
0644     [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
0645     [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
0646     [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
0647     [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
0648     [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
0649     [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
0650     [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
0651     [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
0652     [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
0653     [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
0654     [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
0655     [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
0656     [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
0657     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
0658     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
0659     [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
0660     [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
0661 };
0662 
0663 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
0664     .clks = msm8992_clks,
0665     .num_clks = ARRAY_SIZE(msm8992_clks),
0666 };
0667 
0668 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
0669 
0670 static struct clk_smd_rpm *msm8994_clks[] = {
0671     [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
0672     [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
0673     [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
0674     [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
0675     [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
0676     [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
0677     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
0678     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
0679     [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
0680     [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
0681     [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
0682     [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
0683     [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
0684     [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
0685     [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
0686     [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
0687     [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
0688     [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
0689     [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
0690     [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
0691     [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
0692     [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
0693     [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
0694     [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
0695     [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
0696     [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
0697     [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
0698     [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
0699     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
0700     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
0701     [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
0702     [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
0703     [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
0704     [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
0705     [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
0706     [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
0707     [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
0708     [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
0709     [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
0710     [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
0711     [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
0712     [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
0713     [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
0714     [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
0715     [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
0716     [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
0717     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
0718     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
0719     [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
0720     [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
0721     [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
0722     [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
0723 };
0724 
0725 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
0726     .clks = msm8994_clks,
0727     .num_clks = ARRAY_SIZE(msm8994_clks),
0728 };
0729 
0730 DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
0731            QCOM_SMD_RPM_MMAXI_CLK, 0);
0732 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
0733               QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
0734 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
0735               QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
0736 
0737 static struct clk_smd_rpm *msm8996_clks[] = {
0738     [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
0739     [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
0740     [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
0741     [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
0742     [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
0743     [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
0744     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
0745     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
0746     [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
0747     [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
0748     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
0749     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
0750     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
0751     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
0752     [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
0753     [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
0754     [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
0755     [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
0756     [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
0757     [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
0758     [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
0759     [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
0760     [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
0761     [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
0762     [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
0763     [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
0764     [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
0765     [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
0766     [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
0767     [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
0768     [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
0769     [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
0770     [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
0771     [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
0772     [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
0773     [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
0774     [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
0775     [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
0776     [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
0777     [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
0778     [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
0779     [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
0780     [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
0781     [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
0782 };
0783 
0784 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
0785     .clks = msm8996_clks,
0786     .num_clks = ARRAY_SIZE(msm8996_clks),
0787 };
0788 
0789 DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
0790 DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
0791 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000);
0792 
0793 static struct clk_smd_rpm *qcs404_clks[] = {
0794     [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
0795     [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
0796     [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
0797     [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
0798     [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
0799     [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
0800     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
0801     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
0802     [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk,
0803     [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk,
0804     [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
0805     [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
0806     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
0807     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
0808     [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
0809     [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
0810     [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
0811     [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
0812 };
0813 
0814 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
0815     .clks = qcs404_clks,
0816     .num_clks = ARRAY_SIZE(qcs404_clks),
0817 };
0818 
0819 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
0820 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000);
0821 DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
0822            QCOM_SMD_RPM_AGGR_CLK, 1);
0823 DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
0824            QCOM_SMD_RPM_AGGR_CLK, 2);
0825 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000);
0826 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000);
0827 
0828 static struct clk_smd_rpm *msm8998_clks[] = {
0829     [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
0830     [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
0831     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
0832     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
0833     [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
0834     [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
0835     [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
0836     [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
0837     [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
0838     [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
0839     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
0840     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
0841     [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
0842     [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
0843     [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
0844     [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
0845     [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
0846     [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
0847     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
0848     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
0849     [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
0850     [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
0851     [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
0852     [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
0853     [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
0854     [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
0855     [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
0856     [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
0857     [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
0858     [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
0859     [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
0860     [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
0861     [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
0862     [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
0863     [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
0864     [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
0865     [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
0866     [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
0867     [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
0868     [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
0869     [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
0870     [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
0871     [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
0872     [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
0873     [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
0874     [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
0875     [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
0876     [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
0877     [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
0878     [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
0879     [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
0880     [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
0881 };
0882 
0883 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
0884     .clks = msm8998_clks,
0885     .num_clks = ARRAY_SIZE(msm8998_clks),
0886 };
0887 
0888 static struct clk_smd_rpm *sdm660_clks[] = {
0889     [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
0890     [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
0891     [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
0892     [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
0893     [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
0894     [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
0895     [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk,
0896     [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk,
0897     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
0898     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
0899     [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
0900     [RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk,
0901     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
0902     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
0903     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
0904     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
0905     [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
0906     [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
0907     [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
0908     [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
0909     [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
0910     [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
0911     [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
0912     [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
0913     [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1,
0914     [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
0915     [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
0916     [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
0917     [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
0918     [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
0919     [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
0920     [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
0921     [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
0922     [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
0923     [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
0924     [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
0925     [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
0926     [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
0927 };
0928 
0929 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
0930     .clks = sdm660_clks,
0931     .num_clks = ARRAY_SIZE(sdm660_clks),
0932 };
0933 
0934 static struct clk_smd_rpm *mdm9607_clks[] = {
0935     [RPM_SMD_XO_CLK_SRC]        = &sdm660_bi_tcxo,
0936     [RPM_SMD_XO_A_CLK_SRC]      = &sdm660_bi_tcxo_a,
0937     [RPM_SMD_PCNOC_CLK]     = &msm8916_pcnoc_clk,
0938     [RPM_SMD_PCNOC_A_CLK]       = &msm8916_pcnoc_a_clk,
0939     [RPM_SMD_BIMC_CLK]      = &msm8916_bimc_clk,
0940     [RPM_SMD_BIMC_A_CLK]        = &msm8916_bimc_a_clk,
0941     [RPM_SMD_QPIC_CLK]      = &qcs404_qpic_clk,
0942     [RPM_SMD_QPIC_CLK_A]        = &qcs404_qpic_a_clk,
0943     [RPM_SMD_QDSS_CLK]      = &msm8916_qdss_clk,
0944     [RPM_SMD_QDSS_A_CLK]        = &msm8916_qdss_a_clk,
0945     [RPM_SMD_BB_CLK1]       = &msm8916_bb_clk1,
0946     [RPM_SMD_BB_CLK1_A]     = &msm8916_bb_clk1_a,
0947     [RPM_SMD_BB_CLK1_PIN]       = &msm8916_bb_clk1_pin,
0948     [RPM_SMD_BB_CLK1_A_PIN]     = &msm8916_bb_clk1_a_pin,
0949 };
0950 
0951 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
0952     .clks = mdm9607_clks,
0953     .num_clks = ARRAY_SIZE(mdm9607_clks),
0954 };
0955 
0956 static struct clk_smd_rpm *msm8953_clks[] = {
0957     [RPM_SMD_XO_CLK_SRC]        = &sdm660_bi_tcxo,
0958     [RPM_SMD_XO_A_CLK_SRC]      = &sdm660_bi_tcxo_a,
0959     [RPM_SMD_PCNOC_CLK]     = &msm8916_pcnoc_clk,
0960     [RPM_SMD_PCNOC_A_CLK]       = &msm8916_pcnoc_a_clk,
0961     [RPM_SMD_SNOC_CLK]      = &msm8916_snoc_clk,
0962     [RPM_SMD_SNOC_A_CLK]        = &msm8916_snoc_a_clk,
0963     [RPM_SMD_BIMC_CLK]      = &msm8916_bimc_clk,
0964     [RPM_SMD_BIMC_A_CLK]        = &msm8916_bimc_a_clk,
0965     [RPM_SMD_IPA_CLK]       = &msm8976_ipa_clk,
0966     [RPM_SMD_IPA_A_CLK]     = &msm8976_ipa_a_clk,
0967     [RPM_SMD_SYSMMNOC_CLK]      = &msm8936_sysmmnoc_clk,
0968     [RPM_SMD_SYSMMNOC_A_CLK]    = &msm8936_sysmmnoc_a_clk,
0969     [RPM_SMD_QDSS_CLK]      = &msm8916_qdss_clk,
0970     [RPM_SMD_QDSS_A_CLK]        = &msm8916_qdss_a_clk,
0971     [RPM_SMD_BB_CLK1]       = &msm8916_bb_clk1,
0972     [RPM_SMD_BB_CLK1_A]     = &msm8916_bb_clk1_a,
0973     [RPM_SMD_BB_CLK2]       = &msm8916_bb_clk2,
0974     [RPM_SMD_BB_CLK2_A]     = &msm8916_bb_clk2_a,
0975     [RPM_SMD_RF_CLK2]       = &msm8916_rf_clk2,
0976     [RPM_SMD_RF_CLK2_A]     = &msm8916_rf_clk2_a,
0977     [RPM_SMD_RF_CLK3]       = &msm8992_ln_bb_clk,
0978     [RPM_SMD_RF_CLK3_A]     = &msm8992_ln_bb_a_clk,
0979     [RPM_SMD_DIV_CLK2]      = &msm8974_div_clk2,
0980     [RPM_SMD_DIV_A_CLK2]        = &msm8974_div_a_clk2,
0981     [RPM_SMD_BB_CLK1_PIN]       = &msm8916_bb_clk1_pin,
0982     [RPM_SMD_BB_CLK1_A_PIN]     = &msm8916_bb_clk1_a_pin,
0983     [RPM_SMD_BB_CLK2_PIN]       = &msm8916_bb_clk2_pin,
0984     [RPM_SMD_BB_CLK2_A_PIN]     = &msm8916_bb_clk2_a_pin,
0985 };
0986 
0987 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
0988     .clks = msm8953_clks,
0989     .num_clks = ARRAY_SIZE(msm8953_clks),
0990 };
0991 
0992 /* SM6125 */
0993 DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
0994 DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
0995 DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk,
0996                     QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
0997 DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0);
0998 DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0);
0999 DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1);
1000 DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk,
1001                         QCOM_SMD_RPM_BUS_CLK, 0);
1002 DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk,
1003                         QCOM_SMD_RPM_BUS_CLK, 5);
1004 
1005 static struct clk_smd_rpm *sm6125_clks[] = {
1006     [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1007     [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1008     [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1009     [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1010     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1011     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1012     [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1013     [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1014     [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
1015     [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
1016     [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
1017     [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
1018     [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1019     [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1020     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1021     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1022     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1023     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1024     [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
1025     [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
1026     [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
1027     [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
1028     [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
1029     [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
1030     [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1031     [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1032     [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1033     [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1034     [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1035     [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1036     [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1037     [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1038     [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1039     [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1040 };
1041 
1042 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
1043     .clks = sm6125_clks,
1044     .num_clks = ARRAY_SIZE(sm6125_clks),
1045 };
1046 
1047 /* SM6115 */
1048 static struct clk_smd_rpm *sm6115_clks[] = {
1049     [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1050     [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1051     [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1052     [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1053     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1054     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1055     [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1056     [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1057     [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
1058     [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
1059     [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
1060     [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
1061     [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1062     [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1063     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1064     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1065     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1066     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1067     [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1068     [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1069     [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1070     [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1071     [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1072     [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1073     [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1074     [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1075     [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1076     [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1077     [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
1078     [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
1079     [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
1080     [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
1081 };
1082 
1083 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
1084     .clks = sm6115_clks,
1085     .num_clks = ARRAY_SIZE(sm6115_clks),
1086 };
1087 
1088 /* QCM2290 */
1089 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000);
1090 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000);
1091 
1092 DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
1093 DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
1094 DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);
1095 DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk,
1096            QCOM_SMD_RPM_MEM_CLK, 1);
1097 DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk,
1098            QCOM_SMD_RPM_MEM_CLK, 2);
1099 
1100 static struct clk_smd_rpm *qcm2290_clks[] = {
1101     [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1102     [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1103     [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1104     [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1105     [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1106     [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1107     [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1108     [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1109     [RPM_SMD_LN_BB_CLK2] = &qcm2290_ln_bb_clk2,
1110     [RPM_SMD_LN_BB_CLK2_A] = &qcm2290_ln_bb_clk2_a,
1111     [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3,
1112     [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a,
1113     [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1114     [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1115     [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1116     [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1117     [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1118     [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1119     [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1120     [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1121     [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1122     [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1123     [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1124     [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1125     [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1126     [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1127     [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1128     [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1129     [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk,
1130     [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk,
1131     [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk,
1132     [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk,
1133     [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk,
1134     [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk,
1135     [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk,
1136     [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk,
1137     [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk,
1138     [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk,
1139 };
1140 
1141 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
1142     .clks = qcm2290_clks,
1143     .num_clks = ARRAY_SIZE(qcm2290_clks),
1144 };
1145 
1146 static const struct of_device_id rpm_smd_clk_match_table[] = {
1147     { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
1148     { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
1149     { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
1150     { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
1151     { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
1152     { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
1153     { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
1154     { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
1155     { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
1156     { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
1157     { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
1158     { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },
1159     { .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
1160     { .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
1161     { .compatible = "qcom,rpmcc-sm6115",  .data = &rpm_clk_sm6115  },
1162     { .compatible = "qcom,rpmcc-sm6125",  .data = &rpm_clk_sm6125  },
1163     { }
1164 };
1165 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
1166 
1167 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
1168                          void *data)
1169 {
1170     const struct rpm_smd_clk_desc *desc = data;
1171     unsigned int idx = clkspec->args[0];
1172 
1173     if (idx >= desc->num_clks) {
1174         pr_err("%s: invalid index %u\n", __func__, idx);
1175         return ERR_PTR(-EINVAL);
1176     }
1177 
1178     return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
1179 }
1180 
1181 static int rpm_smd_clk_probe(struct platform_device *pdev)
1182 {
1183     int ret;
1184     size_t num_clks, i;
1185     struct qcom_smd_rpm *rpm;
1186     struct clk_smd_rpm **rpm_smd_clks;
1187     const struct rpm_smd_clk_desc *desc;
1188 
1189     rpm = dev_get_drvdata(pdev->dev.parent);
1190     if (!rpm) {
1191         dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
1192         return -ENODEV;
1193     }
1194 
1195     desc = of_device_get_match_data(&pdev->dev);
1196     if (!desc)
1197         return -EINVAL;
1198 
1199     rpm_smd_clks = desc->clks;
1200     num_clks = desc->num_clks;
1201 
1202     for (i = 0; i < num_clks; i++) {
1203         if (!rpm_smd_clks[i])
1204             continue;
1205 
1206         rpm_smd_clks[i]->rpm = rpm;
1207 
1208         ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
1209         if (ret)
1210             goto err;
1211     }
1212 
1213     ret = clk_smd_rpm_enable_scaling(rpm);
1214     if (ret)
1215         goto err;
1216 
1217     for (i = 0; i < num_clks; i++) {
1218         if (!rpm_smd_clks[i])
1219             continue;
1220 
1221         ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
1222         if (ret)
1223             goto err;
1224     }
1225 
1226     ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
1227                       (void *)desc);
1228     if (ret)
1229         goto err;
1230 
1231     return 0;
1232 err:
1233     dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
1234     return ret;
1235 }
1236 
1237 static struct platform_driver rpm_smd_clk_driver = {
1238     .driver = {
1239         .name = "qcom-clk-smd-rpm",
1240         .of_match_table = rpm_smd_clk_match_table,
1241     },
1242     .probe = rpm_smd_clk_probe,
1243 };
1244 
1245 static int __init rpm_smd_clk_init(void)
1246 {
1247     return platform_driver_register(&rpm_smd_clk_driver);
1248 }
1249 core_initcall(rpm_smd_clk_init);
1250 
1251 static void __exit rpm_smd_clk_exit(void)
1252 {
1253     platform_driver_unregister(&rpm_smd_clk_driver);
1254 }
1255 module_exit(rpm_smd_clk_exit);
1256 
1257 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
1258 MODULE_LICENSE("GPL v2");
1259 MODULE_ALIAS("platform:qcom-clk-smd-rpm");
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