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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016, Linaro Limited
0004  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
0005  */
0006 
0007 #include <linux/clk-provider.h>
0008 #include <linux/err.h>
0009 #include <linux/export.h>
0010 #include <linux/init.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/mutex.h>
0014 #include <linux/mfd/qcom_rpm.h>
0015 #include <linux/of.h>
0016 #include <linux/of_device.h>
0017 #include <linux/platform_device.h>
0018 
0019 #include <dt-bindings/mfd/qcom-rpm.h>
0020 #include <dt-bindings/clock/qcom,rpmcc.h>
0021 
0022 #define QCOM_RPM_MISC_CLK_TYPE              0x306b6c63
0023 #define QCOM_RPM_SCALING_ENABLE_ID          0x2
0024 #define QCOM_RPM_XO_MODE_ON             0x2
0025 
0026 static const struct clk_parent_data gcc_pxo[] = {
0027     { .fw_name = "pxo", .name = "pxo_board" },
0028 };
0029 
0030 static const struct clk_parent_data gcc_cxo[] = {
0031     { .fw_name = "cxo", .name = "cxo_board" },
0032 };
0033 
0034 #define DEFINE_CLK_RPM(_platform, _name, _active, r_id)               \
0035     static struct clk_rpm _platform##_##_active;                  \
0036     static struct clk_rpm _platform##_##_name = {                 \
0037         .rpm_clk_id = (r_id),                         \
0038         .peer = &_platform##_##_active,                   \
0039         .rate = INT_MAX,                          \
0040         .hw.init = &(struct clk_init_data){               \
0041             .ops = &clk_rpm_ops,                      \
0042             .name = #_name,                       \
0043             .parent_data = gcc_pxo,                   \
0044             .num_parents = ARRAY_SIZE(gcc_pxo),           \
0045         },                                \
0046     };                                    \
0047     static struct clk_rpm _platform##_##_active = {               \
0048         .rpm_clk_id = (r_id),                         \
0049         .peer = &_platform##_##_name,                     \
0050         .active_only = true,                          \
0051         .rate = INT_MAX,                          \
0052         .hw.init = &(struct clk_init_data){               \
0053             .ops = &clk_rpm_ops,                      \
0054             .name = #_active,                     \
0055             .parent_data = gcc_pxo,                   \
0056             .num_parents = ARRAY_SIZE(gcc_pxo),           \
0057         },                                \
0058     }
0059 
0060 #define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, _active, offset)       \
0061     static struct clk_rpm _platform##_##_name = {                 \
0062         .rpm_clk_id = QCOM_RPM_CXO_BUFFERS,               \
0063         .xo_offset = (offset),                        \
0064         .hw.init = &(struct clk_init_data){               \
0065             .ops = &clk_rpm_xo_ops,               \
0066             .name = #_name,                       \
0067             .parent_data = gcc_cxo,                   \
0068             .num_parents = ARRAY_SIZE(gcc_cxo),           \
0069         },                                \
0070     }
0071 
0072 #define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r)          \
0073     static struct clk_rpm _platform##_##_name = {                 \
0074         .rpm_clk_id = (r_id),                         \
0075         .rate = (r),                              \
0076         .hw.init = &(struct clk_init_data){               \
0077             .ops = &clk_rpm_fixed_ops,                \
0078             .name = #_name,                       \
0079             .parent_data = gcc_pxo,                   \
0080             .num_parents = ARRAY_SIZE(gcc_pxo),           \
0081         },                                \
0082     }
0083 
0084 #define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
0085 
0086 struct rpm_cc;
0087 
0088 struct clk_rpm {
0089     const int rpm_clk_id;
0090     const int xo_offset;
0091     const bool active_only;
0092     unsigned long rate;
0093     bool enabled;
0094     bool branch;
0095     struct clk_rpm *peer;
0096     struct clk_hw hw;
0097     struct qcom_rpm *rpm;
0098     struct rpm_cc *rpm_cc;
0099 };
0100 
0101 struct rpm_cc {
0102     struct qcom_rpm *rpm;
0103     struct clk_rpm **clks;
0104     size_t num_clks;
0105     u32 xo_buffer_value;
0106     struct mutex xo_lock;
0107 };
0108 
0109 struct rpm_clk_desc {
0110     struct clk_rpm **clks;
0111     size_t num_clks;
0112 };
0113 
0114 static DEFINE_MUTEX(rpm_clk_lock);
0115 
0116 static int clk_rpm_handoff(struct clk_rpm *r)
0117 {
0118     int ret;
0119     u32 value = INT_MAX;
0120 
0121     /*
0122      * The vendor tree simply reads the status for this
0123      * RPM clock.
0124      */
0125     if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||
0126         r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
0127         return 0;
0128 
0129     ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
0130                  r->rpm_clk_id, &value, 1);
0131     if (ret)
0132         return ret;
0133     ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
0134                  r->rpm_clk_id, &value, 1);
0135     if (ret)
0136         return ret;
0137 
0138     return 0;
0139 }
0140 
0141 static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
0142 {
0143     u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
0144 
0145     return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
0146                   r->rpm_clk_id, &value, 1);
0147 }
0148 
0149 static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
0150 {
0151     u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
0152 
0153     return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
0154                   r->rpm_clk_id, &value, 1);
0155 }
0156 
0157 static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
0158                 unsigned long *active, unsigned long *sleep)
0159 {
0160     *active = rate;
0161 
0162     /*
0163      * Active-only clocks don't care what the rate is during sleep. So,
0164      * they vote for zero.
0165      */
0166     if (r->active_only)
0167         *sleep = 0;
0168     else
0169         *sleep = *active;
0170 }
0171 
0172 static int clk_rpm_prepare(struct clk_hw *hw)
0173 {
0174     struct clk_rpm *r = to_clk_rpm(hw);
0175     struct clk_rpm *peer = r->peer;
0176     unsigned long this_rate = 0, this_sleep_rate = 0;
0177     unsigned long peer_rate = 0, peer_sleep_rate = 0;
0178     unsigned long active_rate, sleep_rate;
0179     int ret = 0;
0180 
0181     mutex_lock(&rpm_clk_lock);
0182 
0183     /* Don't send requests to the RPM if the rate has not been set. */
0184     if (!r->rate)
0185         goto out;
0186 
0187     to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
0188 
0189     /* Take peer clock's rate into account only if it's enabled. */
0190     if (peer->enabled)
0191         to_active_sleep(peer, peer->rate,
0192                 &peer_rate, &peer_sleep_rate);
0193 
0194     active_rate = max(this_rate, peer_rate);
0195 
0196     if (r->branch)
0197         active_rate = !!active_rate;
0198 
0199     ret = clk_rpm_set_rate_active(r, active_rate);
0200     if (ret)
0201         goto out;
0202 
0203     sleep_rate = max(this_sleep_rate, peer_sleep_rate);
0204     if (r->branch)
0205         sleep_rate = !!sleep_rate;
0206 
0207     ret = clk_rpm_set_rate_sleep(r, sleep_rate);
0208     if (ret)
0209         /* Undo the active set vote and restore it */
0210         ret = clk_rpm_set_rate_active(r, peer_rate);
0211 
0212 out:
0213     if (!ret)
0214         r->enabled = true;
0215 
0216     mutex_unlock(&rpm_clk_lock);
0217 
0218     return ret;
0219 }
0220 
0221 static void clk_rpm_unprepare(struct clk_hw *hw)
0222 {
0223     struct clk_rpm *r = to_clk_rpm(hw);
0224     struct clk_rpm *peer = r->peer;
0225     unsigned long peer_rate = 0, peer_sleep_rate = 0;
0226     unsigned long active_rate, sleep_rate;
0227     int ret;
0228 
0229     mutex_lock(&rpm_clk_lock);
0230 
0231     if (!r->rate)
0232         goto out;
0233 
0234     /* Take peer clock's rate into account only if it's enabled. */
0235     if (peer->enabled)
0236         to_active_sleep(peer, peer->rate, &peer_rate,
0237                 &peer_sleep_rate);
0238 
0239     active_rate = r->branch ? !!peer_rate : peer_rate;
0240     ret = clk_rpm_set_rate_active(r, active_rate);
0241     if (ret)
0242         goto out;
0243 
0244     sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
0245     ret = clk_rpm_set_rate_sleep(r, sleep_rate);
0246     if (ret)
0247         goto out;
0248 
0249     r->enabled = false;
0250 
0251 out:
0252     mutex_unlock(&rpm_clk_lock);
0253 }
0254 
0255 static int clk_rpm_xo_prepare(struct clk_hw *hw)
0256 {
0257     struct clk_rpm *r = to_clk_rpm(hw);
0258     struct rpm_cc *rcc = r->rpm_cc;
0259     int ret, clk_id = r->rpm_clk_id;
0260     u32 value;
0261 
0262     mutex_lock(&rcc->xo_lock);
0263 
0264     value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);
0265     ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
0266     if (!ret) {
0267         r->enabled = true;
0268         rcc->xo_buffer_value = value;
0269     }
0270 
0271     mutex_unlock(&rcc->xo_lock);
0272 
0273     return ret;
0274 }
0275 
0276 static void clk_rpm_xo_unprepare(struct clk_hw *hw)
0277 {
0278     struct clk_rpm *r = to_clk_rpm(hw);
0279     struct rpm_cc *rcc = r->rpm_cc;
0280     int ret, clk_id = r->rpm_clk_id;
0281     u32 value;
0282 
0283     mutex_lock(&rcc->xo_lock);
0284 
0285     value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
0286     ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
0287     if (!ret) {
0288         r->enabled = false;
0289         rcc->xo_buffer_value = value;
0290     }
0291 
0292     mutex_unlock(&rcc->xo_lock);
0293 }
0294 
0295 static int clk_rpm_fixed_prepare(struct clk_hw *hw)
0296 {
0297     struct clk_rpm *r = to_clk_rpm(hw);
0298     u32 value = 1;
0299     int ret;
0300 
0301     ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
0302                  r->rpm_clk_id, &value, 1);
0303     if (!ret)
0304         r->enabled = true;
0305 
0306     return ret;
0307 }
0308 
0309 static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
0310 {
0311     struct clk_rpm *r = to_clk_rpm(hw);
0312     u32 value = 0;
0313     int ret;
0314 
0315     ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
0316                  r->rpm_clk_id, &value, 1);
0317     if (!ret)
0318         r->enabled = false;
0319 }
0320 
0321 static int clk_rpm_set_rate(struct clk_hw *hw,
0322                 unsigned long rate, unsigned long parent_rate)
0323 {
0324     struct clk_rpm *r = to_clk_rpm(hw);
0325     struct clk_rpm *peer = r->peer;
0326     unsigned long active_rate, sleep_rate;
0327     unsigned long this_rate = 0, this_sleep_rate = 0;
0328     unsigned long peer_rate = 0, peer_sleep_rate = 0;
0329     int ret = 0;
0330 
0331     mutex_lock(&rpm_clk_lock);
0332 
0333     if (!r->enabled)
0334         goto out;
0335 
0336     to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
0337 
0338     /* Take peer clock's rate into account only if it's enabled. */
0339     if (peer->enabled)
0340         to_active_sleep(peer, peer->rate,
0341                 &peer_rate, &peer_sleep_rate);
0342 
0343     active_rate = max(this_rate, peer_rate);
0344     ret = clk_rpm_set_rate_active(r, active_rate);
0345     if (ret)
0346         goto out;
0347 
0348     sleep_rate = max(this_sleep_rate, peer_sleep_rate);
0349     ret = clk_rpm_set_rate_sleep(r, sleep_rate);
0350     if (ret)
0351         goto out;
0352 
0353     r->rate = rate;
0354 
0355 out:
0356     mutex_unlock(&rpm_clk_lock);
0357 
0358     return ret;
0359 }
0360 
0361 static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
0362                    unsigned long *parent_rate)
0363 {
0364     /*
0365      * RPM handles rate rounding and we don't have a way to
0366      * know what the rate will be, so just return whatever
0367      * rate is requested.
0368      */
0369     return rate;
0370 }
0371 
0372 static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
0373                      unsigned long parent_rate)
0374 {
0375     struct clk_rpm *r = to_clk_rpm(hw);
0376 
0377     /*
0378      * RPM handles rate rounding and we don't have a way to
0379      * know what the rate will be, so just return whatever
0380      * rate was set.
0381      */
0382     return r->rate;
0383 }
0384 
0385 static const struct clk_ops clk_rpm_xo_ops = {
0386     .prepare    = clk_rpm_xo_prepare,
0387     .unprepare  = clk_rpm_xo_unprepare,
0388 };
0389 
0390 static const struct clk_ops clk_rpm_fixed_ops = {
0391     .prepare    = clk_rpm_fixed_prepare,
0392     .unprepare  = clk_rpm_fixed_unprepare,
0393     .round_rate = clk_rpm_round_rate,
0394     .recalc_rate    = clk_rpm_recalc_rate,
0395 };
0396 
0397 static const struct clk_ops clk_rpm_ops = {
0398     .prepare    = clk_rpm_prepare,
0399     .unprepare  = clk_rpm_unprepare,
0400     .set_rate   = clk_rpm_set_rate,
0401     .round_rate = clk_rpm_round_rate,
0402     .recalc_rate    = clk_rpm_recalc_rate,
0403 };
0404 
0405 /* MSM8660/APQ8060 */
0406 DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
0407 DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
0408 DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
0409 DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
0410 DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
0411 DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
0412 DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
0413 DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK);
0414 DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
0415 DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000);
0416 
0417 static struct clk_rpm *msm8660_clks[] = {
0418     [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk,
0419     [RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk,
0420     [RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk,
0421     [RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk,
0422     [RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk,
0423     [RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk,
0424     [RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk,
0425     [RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk,
0426     [RPM_SFPB_CLK] = &msm8660_sfpb_clk,
0427     [RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk,
0428     [RPM_CFPB_CLK] = &msm8660_cfpb_clk,
0429     [RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk,
0430     [RPM_MMFPB_CLK] = &msm8660_mmfpb_clk,
0431     [RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk,
0432     [RPM_SMI_CLK] = &msm8660_smi_clk,
0433     [RPM_SMI_A_CLK] = &msm8660_smi_a_clk,
0434     [RPM_EBI1_CLK] = &msm8660_ebi1_clk,
0435     [RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk,
0436     [RPM_PLL4_CLK] = &msm8660_pll4_clk,
0437 };
0438 
0439 static const struct rpm_clk_desc rpm_clk_msm8660 = {
0440     .clks = msm8660_clks,
0441     .num_clks = ARRAY_SIZE(msm8660_clks),
0442 };
0443 
0444 /* apq8064 */
0445 DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
0446 DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
0447 DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
0448 DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
0449 DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
0450 DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
0451 DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
0452 DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
0453 DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
0454 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, xo_d0_a_clk, 0);
0455 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, xo_d1_a_clk, 8);
0456 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, xo_a0_a_clk, 16);
0457 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24);
0458 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28);
0459 
0460 static struct clk_rpm *apq8064_clks[] = {
0461     [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
0462     [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
0463     [RPM_CFPB_CLK] = &apq8064_cfpb_clk,
0464     [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
0465     [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
0466     [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
0467     [RPM_EBI1_CLK] = &apq8064_ebi1_clk,
0468     [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
0469     [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
0470     [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
0471     [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
0472     [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
0473     [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
0474     [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
0475     [RPM_SFPB_CLK] = &apq8064_sfpb_clk,
0476     [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
0477     [RPM_QDSS_CLK] = &apq8064_qdss_clk,
0478     [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
0479     [RPM_XO_D0] = &apq8064_xo_d0_clk,
0480     [RPM_XO_D1] = &apq8064_xo_d1_clk,
0481     [RPM_XO_A0] = &apq8064_xo_a0_clk,
0482     [RPM_XO_A1] = &apq8064_xo_a1_clk,
0483     [RPM_XO_A2] = &apq8064_xo_a2_clk,
0484 };
0485 
0486 static const struct rpm_clk_desc rpm_clk_apq8064 = {
0487     .clks = apq8064_clks,
0488     .num_clks = ARRAY_SIZE(apq8064_clks),
0489 };
0490 
0491 /* ipq806x */
0492 DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
0493 DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
0494 DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
0495 DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
0496 DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
0497 DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
0498 DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
0499 DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
0500 
0501 static struct clk_rpm *ipq806x_clks[] = {
0502     [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
0503     [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
0504     [RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
0505     [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
0506     [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
0507     [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
0508     [RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
0509     [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
0510     [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
0511     [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
0512     [RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
0513     [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
0514     [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
0515     [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
0516     [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
0517     [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
0518 };
0519 
0520 static const struct rpm_clk_desc rpm_clk_ipq806x = {
0521     .clks = ipq806x_clks,
0522     .num_clks = ARRAY_SIZE(ipq806x_clks),
0523 };
0524 
0525 static const struct of_device_id rpm_clk_match_table[] = {
0526     { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
0527     { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
0528     { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
0529     { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
0530     { }
0531 };
0532 MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
0533 
0534 static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
0535                       void *data)
0536 {
0537     struct rpm_cc *rcc = data;
0538     unsigned int idx = clkspec->args[0];
0539 
0540     if (idx >= rcc->num_clks) {
0541         pr_err("%s: invalid index %u\n", __func__, idx);
0542         return ERR_PTR(-EINVAL);
0543     }
0544 
0545     return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
0546 }
0547 
0548 static int rpm_clk_probe(struct platform_device *pdev)
0549 {
0550     struct rpm_cc *rcc;
0551     int ret;
0552     size_t num_clks, i;
0553     struct qcom_rpm *rpm;
0554     struct clk_rpm **rpm_clks;
0555     const struct rpm_clk_desc *desc;
0556 
0557     rpm = dev_get_drvdata(pdev->dev.parent);
0558     if (!rpm) {
0559         dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
0560         return -ENODEV;
0561     }
0562 
0563     desc = of_device_get_match_data(&pdev->dev);
0564     if (!desc)
0565         return -EINVAL;
0566 
0567     rpm_clks = desc->clks;
0568     num_clks = desc->num_clks;
0569 
0570     rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
0571     if (!rcc)
0572         return -ENOMEM;
0573 
0574     rcc->clks = rpm_clks;
0575     rcc->num_clks = num_clks;
0576     mutex_init(&rcc->xo_lock);
0577 
0578     for (i = 0; i < num_clks; i++) {
0579         if (!rpm_clks[i])
0580             continue;
0581 
0582         rpm_clks[i]->rpm = rpm;
0583         rpm_clks[i]->rpm_cc = rcc;
0584 
0585         ret = clk_rpm_handoff(rpm_clks[i]);
0586         if (ret)
0587             goto err;
0588     }
0589 
0590     for (i = 0; i < num_clks; i++) {
0591         if (!rpm_clks[i])
0592             continue;
0593 
0594         ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
0595         if (ret)
0596             goto err;
0597     }
0598 
0599     ret = of_clk_add_hw_provider(pdev->dev.of_node, qcom_rpm_clk_hw_get,
0600                      rcc);
0601     if (ret)
0602         goto err;
0603 
0604     return 0;
0605 err:
0606     dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
0607     return ret;
0608 }
0609 
0610 static int rpm_clk_remove(struct platform_device *pdev)
0611 {
0612     of_clk_del_provider(pdev->dev.of_node);
0613     return 0;
0614 }
0615 
0616 static struct platform_driver rpm_clk_driver = {
0617     .driver = {
0618         .name = "qcom-clk-rpm",
0619         .of_match_table = rpm_clk_match_table,
0620     },
0621     .probe = rpm_clk_probe,
0622     .remove = rpm_clk_remove,
0623 };
0624 
0625 static int __init rpm_clk_init(void)
0626 {
0627     return platform_driver_register(&rpm_clk_driver);
0628 }
0629 core_initcall(rpm_clk_init);
0630 
0631 static void __exit rpm_clk_exit(void)
0632 {
0633     platform_driver_unregister(&rpm_clk_driver);
0634 }
0635 module_exit(rpm_clk_exit);
0636 
0637 MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
0638 MODULE_LICENSE("GPL v2");
0639 MODULE_ALIAS("platform:qcom-clk-rpm");
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