0001
0002
0003
0004
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/bitfield.h>
0008 #include <linux/regmap.h>
0009 #include <linux/export.h>
0010
0011 #include "clk-regmap.h"
0012 #include "clk-regmap-phy-mux.h"
0013
0014 #define PHY_MUX_MASK GENMASK(1, 0)
0015 #define PHY_MUX_PHY_SRC 0
0016 #define PHY_MUX_REF_SRC 2
0017
0018 static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr)
0019 {
0020 return container_of(clkr, struct clk_regmap_phy_mux, clkr);
0021 }
0022
0023 static int phy_mux_is_enabled(struct clk_hw *hw)
0024 {
0025 struct clk_regmap *clkr = to_clk_regmap(hw);
0026 struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
0027 unsigned int val;
0028
0029 regmap_read(clkr->regmap, phy_mux->reg, &val);
0030 val = FIELD_GET(PHY_MUX_MASK, val);
0031
0032 WARN_ON(val != PHY_MUX_PHY_SRC && val != PHY_MUX_REF_SRC);
0033
0034 return val == PHY_MUX_PHY_SRC;
0035 }
0036
0037 static int phy_mux_enable(struct clk_hw *hw)
0038 {
0039 struct clk_regmap *clkr = to_clk_regmap(hw);
0040 struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
0041
0042 return regmap_update_bits(clkr->regmap, phy_mux->reg,
0043 PHY_MUX_MASK,
0044 FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC));
0045 }
0046
0047 static void phy_mux_disable(struct clk_hw *hw)
0048 {
0049 struct clk_regmap *clkr = to_clk_regmap(hw);
0050 struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
0051
0052 regmap_update_bits(clkr->regmap, phy_mux->reg,
0053 PHY_MUX_MASK,
0054 FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC));
0055 }
0056
0057 const struct clk_ops clk_regmap_phy_mux_ops = {
0058 .enable = phy_mux_enable,
0059 .disable = phy_mux_disable,
0060 .is_enabled = phy_mux_is_enabled,
0061 };
0062 EXPORT_SYMBOL_GPL(clk_regmap_phy_mux_ops);