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0006 #include <linux/kernel.h>
0007 #include <linux/bitops.h>
0008 #include <linux/regmap.h>
0009 #include <linux/export.h>
0010
0011 #include "clk-regmap-mux.h"
0012
0013 static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw)
0014 {
0015 return container_of(to_clk_regmap(hw), struct clk_regmap_mux, clkr);
0016 }
0017
0018 static u8 mux_get_parent(struct clk_hw *hw)
0019 {
0020 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
0021 struct clk_regmap *clkr = to_clk_regmap(hw);
0022 unsigned int mask = GENMASK(mux->width - 1, 0);
0023 unsigned int val;
0024
0025 regmap_read(clkr->regmap, mux->reg, &val);
0026
0027 val >>= mux->shift;
0028 val &= mask;
0029
0030 if (mux->parent_map)
0031 return qcom_find_cfg_index(hw, mux->parent_map, val);
0032
0033 return val;
0034 }
0035
0036 static int mux_set_parent(struct clk_hw *hw, u8 index)
0037 {
0038 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
0039 struct clk_regmap *clkr = to_clk_regmap(hw);
0040 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
0041 unsigned int val;
0042
0043 if (mux->parent_map)
0044 index = mux->parent_map[index].cfg;
0045
0046 val = index;
0047 val <<= mux->shift;
0048
0049 return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
0050 }
0051
0052 const struct clk_ops clk_regmap_mux_closest_ops = {
0053 .get_parent = mux_get_parent,
0054 .set_parent = mux_set_parent,
0055 .determine_rate = __clk_mux_determine_rate_closest,
0056 };
0057 EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);