clk/qcom/clk-regmap-divider.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/kernel.h>
0007 #include <linux/bitops.h>
0008 #include <linux/regmap.h>
0009 #include <linux/export.h>
0010
0011 #include "clk-regmap-divider.h"
0012
0013 static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
0014 {
0015     return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
0016 }
0017
0018 static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
0019                   unsigned long *prate)
0020 {
0021     struct clk_regmap_div *divider = to_clk_regmap_div(hw);
0022     struct clk_regmap *clkr = &divider->clkr;
0023     u32 val;
0024
0025     regmap_read(clkr->regmap, divider->reg, &val);
0026     val >>= divider->shift;
0027     val &= BIT(divider->width) - 1;
0028
0029     return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
0030                      CLK_DIVIDER_ROUND_CLOSEST, val);
0031 }
0032
0033 static long div_round_rate(struct clk_hw *hw, unsigned long rate,
0034                unsigned long *prate)
0035 {
0036     struct clk_regmap_div *divider = to_clk_regmap_div(hw);
0037
0038     return divider_round_rate(hw, rate, prate, NULL, divider->width,
0039                   CLK_DIVIDER_ROUND_CLOSEST);
0040 }
0041
0042 static int div_set_rate(struct clk_hw *hw, unsigned long rate,
0043             unsigned long parent_rate)
0044 {
0045     struct clk_regmap_div *divider = to_clk_regmap_div(hw);
0046     struct clk_regmap *clkr = &divider->clkr;
0047     u32 div;
0048
0049     div = divider_get_val(rate, parent_rate, NULL, divider->width,
0050                   CLK_DIVIDER_ROUND_CLOSEST);
0051
0052     return regmap_update_bits(clkr->regmap, divider->reg,
0053                   (BIT(divider->width) - 1) << divider->shift,
0054                   div << divider->shift);
0055 }
0056
0057 static unsigned long div_recalc_rate(struct clk_hw *hw,
0058                      unsigned long parent_rate)
0059 {
0060     struct clk_regmap_div *divider = to_clk_regmap_div(hw);
0061     struct clk_regmap *clkr = &divider->clkr;
0062     u32 div;
0063
0064     regmap_read(clkr->regmap, divider->reg, &div);
0065     div >>= divider->shift;
0066     div &= BIT(divider->width) - 1;
0067
0068     return divider_recalc_rate(hw, parent_rate, div, NULL,
0069                    CLK_DIVIDER_ROUND_CLOSEST, divider->width);
0070 }
0071
0072 const struct clk_ops clk_regmap_div_ops = {
0073     .round_rate = div_round_rate,
0074     .set_rate = div_set_rate,
0075     .recalc_rate = div_recalc_rate,
0076 };
0077 EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
0078
0079 const struct clk_ops clk_regmap_div_ro_ops = {
0080     .round_rate = div_round_ro_rate,
0081     .recalc_rate = div_recalc_rate,
0082 };
0083 EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);