clk/qcom/clk-rcg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
0003
0004 #ifndef __QCOM_CLK_RCG_H__
0005 #define __QCOM_CLK_RCG_H__
0006
0007 #include <linux/clk-provider.h>
0008 #include "clk-regmap.h"
0009
0010 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
0011
0012 struct freq_tbl {
0013     unsigned long freq;
0014     u8 src;
0015     u8 pre_div;
0016     u16 m;
0017     u16 n;
0018 };
0019
0020 /**
0021  * struct mn - M/N:D counter
0022  * @mnctr_en_bit: bit to enable mn counter
0023  * @mnctr_reset_bit: bit to assert mn counter reset
0024  * @mnctr_mode_shift: lowest bit of mn counter mode field
0025  * @n_val_shift: lowest bit of n value field
0026  * @m_val_shift: lowest bit of m value field
0027  * @width: number of bits in m/n/d values
0028  * @reset_in_cc: true if the mnctr_reset_bit is in the CC register
0029  */
0030 struct mn {
0031     u8      mnctr_en_bit;
0032     u8      mnctr_reset_bit;
0033     u8      mnctr_mode_shift;
0034 #define MNCTR_MODE_DUAL 0x2
0035 #define MNCTR_MODE_MASK 0x3
0036     u8      n_val_shift;
0037     u8      m_val_shift;
0038     u8      width;
0039     bool        reset_in_cc;
0040 };
0041
0042 /**
0043  * struct pre_div - pre-divider
0044  * @pre_div_shift: lowest bit of pre divider field
0045  * @pre_div_width: number of bits in predivider
0046  */
0047 struct pre_div {
0048     u8      pre_div_shift;
0049     u8      pre_div_width;
0050 };
0051
0052 /**
0053  * struct src_sel - source selector
0054  * @src_sel_shift: lowest bit of source selection field
0055  * @parent_map: map from software's parent index to hardware's src_sel field
0056  */
0057 struct src_sel {
0058     u8      src_sel_shift;
0059 #define SRC_SEL_MASK    0x7
0060     const struct parent_map *parent_map;
0061 };
0062
0063 /**
0064  * struct clk_rcg - root clock generator
0065  *
0066  * @ns_reg: NS register
0067  * @md_reg: MD register
0068  * @mn: mn counter
0069  * @p: pre divider
0070  * @s: source selector
0071  * @freq_tbl: frequency table
0072  * @clkr: regmap clock handle
0073  * @lock: register lock
0074  */
0075 struct clk_rcg {
0076     u32     ns_reg;
0077     u32     md_reg;
0078
0079     struct mn   mn;
0080     struct pre_div  p;
0081     struct src_sel  s;
0082
0083     const struct freq_tbl   *freq_tbl;
0084
0085     struct clk_regmap   clkr;
0086 };
0087
0088 extern const struct clk_ops clk_rcg_ops;
0089 extern const struct clk_ops clk_rcg_floor_ops;
0090 extern const struct clk_ops clk_rcg_bypass_ops;
0091 extern const struct clk_ops clk_rcg_bypass2_ops;
0092 extern const struct clk_ops clk_rcg_pixel_ops;
0093 extern const struct clk_ops clk_rcg_esc_ops;
0094 extern const struct clk_ops clk_rcg_lcc_ops;
0095
0096 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
0097
0098 /**
0099  * struct clk_dyn_rcg - root clock generator with glitch free mux
0100  *
0101  * @mux_sel_bit: bit to switch glitch free mux
0102  * @ns_reg: NS0 and NS1 register
0103  * @md_reg: MD0 and MD1 register
0104  * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
0105  * @mn: mn counter (banked)
0106  * @s: source selector (banked)
0107  * @freq_tbl: frequency table
0108  * @clkr: regmap clock handle
0109  * @lock: register lock
0110  */
0111 struct clk_dyn_rcg {
0112     u32 ns_reg[2];
0113     u32 md_reg[2];
0114     u32 bank_reg;
0115
0116     u8  mux_sel_bit;
0117
0118     struct mn   mn[2];
0119     struct pre_div  p[2];
0120     struct src_sel  s[2];
0121
0122     const struct freq_tbl *freq_tbl;
0123
0124     struct clk_regmap clkr;
0125 };
0126
0127 extern const struct clk_ops clk_dyn_rcg_ops;
0128
0129 #define to_clk_dyn_rcg(_hw) \
0130     container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
0131
0132 /**
0133  * struct clk_rcg2 - root clock generator
0134  *
0135  * @cmd_rcgr: corresponds to *_CMD_RCGR
0136  * @mnd_width: number of bits in m/n/d values
0137  * @hid_width: number of bits in half integer divider
0138  * @safe_src_index: safe src index value
0139  * @parent_map: map from software's parent index to hardware's src_sel field
0140  * @freq_tbl: frequency table
0141  * @clkr: regmap clock handle
0142  * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
0143  * @parked_cfg: cached value of the CFG register for parked RCGs
0144  */
0145 struct clk_rcg2 {
0146     u32         cmd_rcgr;
0147     u8          mnd_width;
0148     u8          hid_width;
0149     u8          safe_src_index;
0150     const struct parent_map *parent_map;
0151     const struct freq_tbl   *freq_tbl;
0152     struct clk_regmap   clkr;
0153     u8          cfg_off;
0154     u32         parked_cfg;
0155 };
0156
0157 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
0158
0159 struct clk_rcg2_gfx3d {
0160     u8 div;
0161     struct clk_rcg2 rcg;
0162     struct clk_hw **hws;
0163 };
0164
0165 #define to_clk_rcg2_gfx3d(_hw) \
0166     container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg)
0167
0168 extern const struct clk_ops clk_rcg2_ops;
0169 extern const struct clk_ops clk_rcg2_floor_ops;
0170 extern const struct clk_ops clk_edp_pixel_ops;
0171 extern const struct clk_ops clk_byte_ops;
0172 extern const struct clk_ops clk_byte2_ops;
0173 extern const struct clk_ops clk_pixel_ops;
0174 extern const struct clk_ops clk_gfx3d_ops;
0175 extern const struct clk_ops clk_rcg2_shared_ops;
0176 extern const struct clk_ops clk_dp_ops;
0177
0178 struct clk_rcg_dfs_data {
0179     struct clk_rcg2 *rcg;
0180     struct clk_init_data *init;
0181 };
0182
0183 #define DEFINE_RCG_DFS(r) \
0184     { .rcg = &r, .init = &r##_init }
0185
0186 extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
0187                     const struct clk_rcg_dfs_data *rcgs,
0188                     size_t len);
0189 #endif