clk/qcom/clk-hfpll.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef __QCOM_CLK_HFPLL_H__
0004 #define __QCOM_CLK_HFPLL_H__
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/spinlock.h>
0008 #include "clk-regmap.h"
0009
0010 struct hfpll_data {
0011     u32 mode_reg;
0012     u32 l_reg;
0013     u32 m_reg;
0014     u32 n_reg;
0015     u32 user_reg;
0016     u32 droop_reg;
0017     u32 config_reg;
0018     u32 status_reg;
0019     u8  lock_bit;
0020
0021     u32 droop_val;
0022     u32 config_val;
0023     u32 user_val;
0024     u32 user_vco_mask;
0025     unsigned long low_vco_max_rate;
0026
0027     unsigned long min_rate;
0028     unsigned long max_rate;
0029 };
0030
0031 struct clk_hfpll {
0032     struct hfpll_data const *d;
0033     int init_done;
0034
0035     struct clk_regmap clkr;
0036     spinlock_t lock;
0037 };
0038
0039 #define to_clk_hfpll(_hw) \
0040     container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr)
0041
0042 extern const struct clk_ops clk_ops_hfpll;
0043
0044 #endif