clk/qcom/clk-alpha-pll.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
0003
0004 #ifndef __QCOM_CLK_ALPHA_PLL_H__
0005 #define __QCOM_CLK_ALPHA_PLL_H__
0006
0007 #include <linux/clk-provider.h>
0008 #include "clk-regmap.h"
0009
0010 /* Alpha PLL types */
0011 enum {
0012     CLK_ALPHA_PLL_TYPE_DEFAULT,
0013     CLK_ALPHA_PLL_TYPE_HUAYRA,
0014     CLK_ALPHA_PLL_TYPE_BRAMMO,
0015     CLK_ALPHA_PLL_TYPE_FABIA,
0016     CLK_ALPHA_PLL_TYPE_TRION,
0017     CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
0018     CLK_ALPHA_PLL_TYPE_AGERA,
0019     CLK_ALPHA_PLL_TYPE_ZONDA,
0020     CLK_ALPHA_PLL_TYPE_LUCID_EVO,
0021     CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
0022     CLK_ALPHA_PLL_TYPE_MAX,
0023 };
0024
0025 enum {
0026     PLL_OFF_L_VAL,
0027     PLL_OFF_CAL_L_VAL,
0028     PLL_OFF_ALPHA_VAL,
0029     PLL_OFF_ALPHA_VAL_U,
0030     PLL_OFF_USER_CTL,
0031     PLL_OFF_USER_CTL_U,
0032     PLL_OFF_USER_CTL_U1,
0033     PLL_OFF_CONFIG_CTL,
0034     PLL_OFF_CONFIG_CTL_U,
0035     PLL_OFF_CONFIG_CTL_U1,
0036     PLL_OFF_TEST_CTL,
0037     PLL_OFF_TEST_CTL_U,
0038     PLL_OFF_TEST_CTL_U1,
0039     PLL_OFF_STATUS,
0040     PLL_OFF_OPMODE,
0041     PLL_OFF_FRAC,
0042     PLL_OFF_CAL_VAL,
0043     PLL_OFF_MAX_REGS
0044 };
0045
0046 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
0047
0048 struct pll_vco {
0049     unsigned long min_freq;
0050     unsigned long max_freq;
0051     u32 val;
0052 };
0053
0054 #define VCO(a, b, c) { \
0055     .val = a,\
0056     .min_freq = b,\
0057     .max_freq = c,\
0058 }
0059
0060 /**
0061  * struct clk_alpha_pll - phase locked loop (PLL)
0062  * @offset: base address of registers
0063  * @vco_table: array of VCO settings
0064  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
0065  * @clkr: regmap clock handle
0066  */
0067 struct clk_alpha_pll {
0068     u32 offset;
0069     const u8 *regs;
0070
0071     const struct pll_vco *vco_table;
0072     size_t num_vco;
0073 #define SUPPORTS_OFFLINE_REQ    BIT(0)
0074 #define SUPPORTS_FSM_MODE   BIT(2)
0075 #define SUPPORTS_DYNAMIC_UPDATE BIT(3)
0076     u8 flags;
0077
0078     struct clk_regmap clkr;
0079 };
0080
0081 /**
0082  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
0083  * @offset: base address of registers
0084  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
0085  * @width: width of post-divider
0086  * @post_div_shift: shift to differentiate between odd & even post-divider
0087  * @post_div_table: table with PLL odd and even post-divider settings
0088  * @num_post_div: Number of PLL post-divider settings
0089  *
0090  * @clkr: regmap clock handle
0091  */
0092 struct clk_alpha_pll_postdiv {
0093     u32 offset;
0094     u8 width;
0095     const u8 *regs;
0096
0097     struct clk_regmap clkr;
0098     int post_div_shift;
0099     const struct clk_div_table *post_div_table;
0100     size_t num_post_div;
0101 };
0102
0103 struct alpha_pll_config {
0104     u32 l;
0105     u32 alpha;
0106     u32 alpha_hi;
0107     u32 config_ctl_val;
0108     u32 config_ctl_hi_val;
0109     u32 config_ctl_hi1_val;
0110     u32 user_ctl_val;
0111     u32 user_ctl_hi_val;
0112     u32 user_ctl_hi1_val;
0113     u32 test_ctl_val;
0114     u32 test_ctl_hi_val;
0115     u32 test_ctl_hi1_val;
0116     u32 main_output_mask;
0117     u32 aux_output_mask;
0118     u32 aux2_output_mask;
0119     u32 early_output_mask;
0120     u32 alpha_en_mask;
0121     u32 alpha_mode_mask;
0122     u32 pre_div_val;
0123     u32 pre_div_mask;
0124     u32 post_div_val;
0125     u32 post_div_mask;
0126     u32 vco_val;
0127     u32 vco_mask;
0128 };
0129
0130 extern const struct clk_ops clk_alpha_pll_ops;
0131 extern const struct clk_ops clk_alpha_pll_fixed_ops;
0132 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
0133 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
0134 extern const struct clk_ops clk_alpha_pll_huayra_ops;
0135 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
0136
0137 extern const struct clk_ops clk_alpha_pll_fabia_ops;
0138 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
0139 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
0140
0141 extern const struct clk_ops clk_alpha_pll_trion_ops;
0142 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
0143 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
0144
0145 extern const struct clk_ops clk_alpha_pll_lucid_ops;
0146 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
0147 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
0148 extern const struct clk_ops clk_alpha_pll_agera_ops;
0149
0150 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
0151 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
0152 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
0153
0154 extern const struct clk_ops clk_alpha_pll_zonda_ops;
0155 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
0156
0157 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
0158 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
0159 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
0160
0161 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
0162 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
0163
0164 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
0165                  const struct alpha_pll_config *config);
0166 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
0167                 const struct alpha_pll_config *config);
0168 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
0169                  const struct alpha_pll_config *config);
0170 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
0171                 const struct alpha_pll_config *config);
0172 #define clk_lucid_pll_configure(pll, regmap, config) \
0173     clk_trion_pll_configure(pll, regmap, config)
0174
0175 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
0176                  const struct alpha_pll_config *config);
0177 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
0178                  const struct alpha_pll_config *config);
0179 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
0180                   const struct alpha_pll_config *config);
0181
0182 #endif