clk/qcom/apss-ipq-pll.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2018, The Linux Foundation. All rights reserved.
0003 #include <linux/clk-provider.h>
0004 #include <linux/module.h>
0005 #include <linux/platform_device.h>
0006 #include <linux/regmap.h>
0007
0008 #include "clk-alpha-pll.h"
0009
0010 static const u8 ipq_pll_offsets[] = {
0011     [PLL_OFF_L_VAL] = 0x08,
0012     [PLL_OFF_ALPHA_VAL] = 0x10,
0013     [PLL_OFF_USER_CTL] = 0x18,
0014     [PLL_OFF_CONFIG_CTL] = 0x20,
0015     [PLL_OFF_CONFIG_CTL_U] = 0x24,
0016     [PLL_OFF_STATUS] = 0x28,
0017     [PLL_OFF_TEST_CTL] = 0x30,
0018     [PLL_OFF_TEST_CTL_U] = 0x34,
0019 };
0020
0021 static struct clk_alpha_pll ipq_pll = {
0022     .offset = 0x0,
0023     .regs = ipq_pll_offsets,
0024     .flags = SUPPORTS_DYNAMIC_UPDATE,
0025     .clkr = {
0026         .enable_reg = 0x0,
0027         .enable_mask = BIT(0),
0028         .hw.init = &(struct clk_init_data){
0029             .name = "a53pll",
0030             .parent_data = &(const struct clk_parent_data) {
0031                 .fw_name = "xo",
0032             },
0033             .num_parents = 1,
0034             .ops = &clk_alpha_pll_huayra_ops,
0035         },
0036     },
0037 };
0038
0039 static const struct alpha_pll_config ipq_pll_config = {
0040     .l = 0x37,
0041     .config_ctl_val = 0x04141200,
0042     .config_ctl_hi_val = 0x0,
0043     .early_output_mask = BIT(3),
0044     .main_output_mask = BIT(0),
0045 };
0046
0047 static const struct regmap_config ipq_pll_regmap_config = {
0048     .reg_bits       = 32,
0049     .reg_stride     = 4,
0050     .val_bits       = 32,
0051     .max_register       = 0x40,
0052     .fast_io        = true,
0053 };
0054
0055 static int apss_ipq_pll_probe(struct platform_device *pdev)
0056 {
0057     struct device *dev = &pdev->dev;
0058     struct regmap *regmap;
0059     void __iomem *base;
0060     int ret;
0061
0062     base = devm_platform_ioremap_resource(pdev, 0);
0063     if (IS_ERR(base))
0064         return PTR_ERR(base);
0065
0066     regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);
0067     if (IS_ERR(regmap))
0068         return PTR_ERR(regmap);
0069
0070     clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
0071
0072     ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
0073     if (ret)
0074         return ret;
0075
0076     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
0077                        &ipq_pll.clkr.hw);
0078 }
0079
0080 static const struct of_device_id apss_ipq_pll_match_table[] = {
0081     { .compatible = "qcom,ipq6018-a53pll" },
0082     { }
0083 };
0084 MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
0085
0086 static struct platform_driver apss_ipq_pll_driver = {
0087     .probe = apss_ipq_pll_probe,
0088     .driver = {
0089         .name = "qcom-ipq-apss-pll",
0090         .of_match_table = apss_ipq_pll_match_table,
0091     },
0092 };
0093 module_platform_driver(apss_ipq_pll_driver);
0094
0095 MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
0096 MODULE_LICENSE("GPL v2");