clk/qcom/apcs-msm8916.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Qualcomm APCS clock controller driver
0004  *
0005  * Copyright (c) 2017, Linaro Limited
0006  * Author: Georgi Djakov <georgi.djakov@linaro.org>
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/slab.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016
0017 #include "clk-regmap.h"
0018 #include "clk-regmap-mux-div.h"
0019
0020 static const u32 gpll0_a53cc_map[] = { 4, 5 };
0021
0022 static const struct clk_parent_data pdata[] = {
0023     { .fw_name = "aux", .name = "gpll0_vote", },
0024     { .fw_name = "pll", .name = "a53pll", },
0025 };
0026
0027 /*
0028  * We use the notifier function for switching to a temporary safe configuration
0029  * (mux and divider), while the A53 PLL is reconfigured.
0030  */
0031 static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event,
0032                  void *data)
0033 {
0034     int ret = 0;
0035     struct clk_regmap_mux_div *md = container_of(nb,
0036                              struct clk_regmap_mux_div,
0037                              clk_nb);
0038     if (event == PRE_RATE_CHANGE)
0039         /* set the mux and divider to safe frequency (400mhz) */
0040         ret = mux_div_set_src_div(md, 4, 3);
0041
0042     return notifier_from_errno(ret);
0043 }
0044
0045 static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
0046 {
0047     struct device *dev = &pdev->dev;
0048     struct device *parent = dev->parent;
0049     struct device_node *np = parent->of_node;
0050     struct clk_regmap_mux_div *a53cc;
0051     struct regmap *regmap;
0052     struct clk_init_data init = { };
0053     int ret = -ENODEV;
0054
0055     regmap = dev_get_regmap(parent, NULL);
0056     if (!regmap) {
0057         dev_err(dev, "failed to get regmap: %d\n", ret);
0058         return ret;
0059     }
0060
0061     a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL);
0062     if (!a53cc)
0063         return -ENOMEM;
0064
0065     /* Use an unique name by appending parent's @unit-address */
0066     init.name = devm_kasprintf(dev, GFP_KERNEL, "a53mux%s",
0067                    strchrnul(np->full_name, '@'));
0068     if (!init.name)
0069         return -ENOMEM;
0070
0071     init.parent_data = pdata;
0072     init.num_parents = ARRAY_SIZE(pdata);
0073     init.ops = &clk_regmap_mux_div_ops;
0074     init.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT;
0075
0076     a53cc->clkr.hw.init = &init;
0077     a53cc->clkr.regmap = regmap;
0078     a53cc->reg_offset = 0x50;
0079     a53cc->hid_width = 5;
0080     a53cc->hid_shift = 0;
0081     a53cc->src_width = 3;
0082     a53cc->src_shift = 8;
0083     a53cc->parent_map = gpll0_a53cc_map;
0084
0085     a53cc->pclk = devm_clk_get(parent, NULL);
0086     if (IS_ERR(a53cc->pclk)) {
0087         ret = PTR_ERR(a53cc->pclk);
0088         if (ret != -EPROBE_DEFER)
0089             dev_err(dev, "failed to get clk: %d\n", ret);
0090         return ret;
0091     }
0092
0093     a53cc->clk_nb.notifier_call = a53cc_notifier_cb;
0094     ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
0095     if (ret) {
0096         dev_err(dev, "failed to register clock notifier: %d\n", ret);
0097         return ret;
0098     }
0099
0100     ret = devm_clk_register_regmap(dev, &a53cc->clkr);
0101     if (ret) {
0102         dev_err(dev, "failed to register regmap clock: %d\n", ret);
0103         goto err;
0104     }
0105
0106     ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
0107                       &a53cc->clkr.hw);
0108     if (ret) {
0109         dev_err(dev, "failed to add clock provider: %d\n", ret);
0110         goto err;
0111     }
0112
0113     platform_set_drvdata(pdev, a53cc);
0114
0115     return 0;
0116
0117 err:
0118     clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
0119     return ret;
0120 }
0121
0122 static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
0123 {
0124     struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
0125
0126     clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
0127
0128     return 0;
0129 }
0130
0131 static struct platform_driver qcom_apcs_msm8916_clk_driver = {
0132     .probe = qcom_apcs_msm8916_clk_probe,
0133     .remove = qcom_apcs_msm8916_clk_remove,
0134     .driver = {
0135         .name = "qcom-apcs-msm8916-clk",
0136     },
0137 };
0138 module_platform_driver(qcom_apcs_msm8916_clk_driver);
0139
0140 MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
0141 MODULE_LICENSE("GPL v2");
0142 MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");