clk/qcom/a7-pll.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Qualcomm A7 PLL driver
0004  *
0005  * Copyright (c) 2020, Linaro Limited
0006  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0007  */
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/regmap.h>
0013
0014 #include "clk-alpha-pll.h"
0015
0016 #define LUCID_PLL_OFF_L_VAL 0x04
0017
0018 static const struct pll_vco lucid_vco[] = {
0019     { 249600000, 2000000000, 0 },
0020 };
0021
0022 static struct clk_alpha_pll a7pll = {
0023     .offset = 0x100,
0024     .vco_table = lucid_vco,
0025     .num_vco = ARRAY_SIZE(lucid_vco),
0026     .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
0027     .clkr = {
0028         .hw.init = &(struct clk_init_data){
0029             .name = "a7pll",
0030             .parent_data =  &(const struct clk_parent_data){
0031                 .fw_name = "bi_tcxo",
0032             },
0033             .num_parents = 1,
0034             .ops = &clk_alpha_pll_lucid_ops,
0035         },
0036     },
0037 };
0038
0039 static const struct alpha_pll_config a7pll_config = {
0040     .l = 0x39,
0041     .config_ctl_val = 0x20485699,
0042     .config_ctl_hi_val = 0x2261,
0043     .config_ctl_hi1_val = 0x029A699C,
0044     .user_ctl_val = 0x1,
0045     .user_ctl_hi_val = 0x805,
0046 };
0047
0048 static const struct regmap_config a7pll_regmap_config = {
0049     .reg_bits       = 32,
0050     .reg_stride     = 4,
0051     .val_bits       = 32,
0052     .max_register       = 0x1000,
0053     .fast_io        = true,
0054 };
0055
0056 static int qcom_a7pll_probe(struct platform_device *pdev)
0057 {
0058     struct device *dev = &pdev->dev;
0059     struct regmap *regmap;
0060     void __iomem *base;
0061     u32 l_val;
0062     int ret;
0063
0064     base = devm_platform_ioremap_resource(pdev, 0);
0065     if (IS_ERR(base))
0066         return PTR_ERR(base);
0067
0068     regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config);
0069     if (IS_ERR(regmap))
0070         return PTR_ERR(regmap);
0071
0072     /* Configure PLL only if the l_val is zero */
0073     regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val);
0074     if (!l_val)
0075         clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config);
0076
0077     ret = devm_clk_register_regmap(dev, &a7pll.clkr);
0078     if (ret)
0079         return ret;
0080
0081     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
0082                        &a7pll.clkr.hw);
0083 }
0084
0085 static const struct of_device_id qcom_a7pll_match_table[] = {
0086     { .compatible = "qcom,sdx55-a7pll" },
0087     { }
0088 };
0089 MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
0090
0091 static struct platform_driver qcom_a7pll_driver = {
0092     .probe = qcom_a7pll_probe,
0093     .driver = {
0094         .name = "qcom-a7pll",
0095         .of_match_table = qcom_a7pll_match_table,
0096     },
0097 };
0098 module_platform_driver(qcom_a7pll_driver);
0099
0100 MODULE_DESCRIPTION("Qualcomm A7 PLL Driver");
0101 MODULE_LICENSE("GPL v2");