clk/pxa/clk-pxa3xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Marvell PXA3xxx family clocks
0004  *
0005  * Copyright (C) 2014 Robert Jarzmik
0006  *
0007  * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
0008  *
0009  * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
0010  * should go away.
0011  */
0012 #include <linux/io.h>
0013 #include <linux/clk.h>
0014 #include <linux/clk-provider.h>
0015 #include <linux/clkdev.h>
0016 #include <linux/of.h>
0017 #include <linux/soc/pxa/cpu.h>
0018 #include <linux/soc/pxa/smemc.h>
0019 #include <linux/clk/pxa.h>
0020
0021 #include <dt-bindings/clock/pxa-clock.h>
0022 #include "clk-pxa.h"
0023
0024 #define KHz 1000
0025 #define MHz (1000 * 1000)
0026
0027 #define ACCR            (0x0000)    /* Application Subsystem Clock Configuration Register */
0028 #define ACSR            (0x0004)    /* Application Subsystem Clock Status Register */
0029 #define AICSR           (0x0008)    /* Application Subsystem Interrupt Control/Status Register */
0030 #define CKENA           (0x000C)    /* A Clock Enable Register */
0031 #define CKENB           (0x0010)    /* B Clock Enable Register */
0032 #define CKENC           (0x0024)    /* C Clock Enable Register */
0033 #define AC97_DIV        (0x0014)    /* AC97 clock divisor value register */
0034
0035 #define ACCR_XPDIS      (1 << 31)   /* Core PLL Output Disable */
0036 #define ACCR_SPDIS      (1 << 30)   /* System PLL Output Disable */
0037 #define ACCR_D0CS       (1 << 26)   /* D0 Mode Clock Select */
0038 #define ACCR_PCCE       (1 << 11)   /* Power Mode Change Clock Enable */
0039 #define ACCR_DDR_D0CS       (1 << 7)    /* DDR SDRAM clock frequency in D0CS (PXA31x only) */
0040
0041 #define ACCR_SMCFS_MASK     (0x7 << 23) /* Static Memory Controller Frequency Select */
0042 #define ACCR_SFLFS_MASK     (0x3 << 18) /* Frequency Select for Internal Memory Controller */
0043 #define ACCR_XSPCLK_MASK    (0x3 << 16) /* Core Frequency during Frequency Change */
0044 #define ACCR_HSS_MASK       (0x3 << 14) /* System Bus-Clock Frequency Select */
0045 #define ACCR_DMCFS_MASK     (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */
0046 #define ACCR_XN_MASK        (0x7 << 8)  /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
0047 #define ACCR_XL_MASK        (0x1f)      /* Core PLL Run-Mode-to-Oscillator Ratio */
0048
0049 #define ACCR_SMCFS(x)       (((x) & 0x7) << 23)
0050 #define ACCR_SFLFS(x)       (((x) & 0x3) << 18)
0051 #define ACCR_XSPCLK(x)      (((x) & 0x3) << 16)
0052 #define ACCR_HSS(x)     (((x) & 0x3) << 14)
0053 #define ACCR_DMCFS(x)       (((x) & 0x3) << 12)
0054 #define ACCR_XN(x)      (((x) & 0x7) << 8)
0055 #define ACCR_XL(x)      ((x) & 0x1f)
0056
0057 /*
0058  * Clock Enable Bit
0059  */
0060 #define CKEN_LCD    1   /* < LCD Clock Enable */
0061 #define CKEN_USBH   2   /* < USB host clock enable */
0062 #define CKEN_CAMERA 3   /* < Camera interface clock enable */
0063 #define CKEN_NAND   4   /* < NAND Flash Controller Clock Enable */
0064 #define CKEN_USB2   6   /* < USB 2.0 client clock enable. */
0065 #define CKEN_DMC    8   /* < Dynamic Memory Controller clock enable */
0066 #define CKEN_SMC    9   /* < Static Memory Controller clock enable */
0067 #define CKEN_ISC    10  /* < Internal SRAM Controller clock enable */
0068 #define CKEN_BOOT   11  /* < Boot rom clock enable */
0069 #define CKEN_MMC1   12  /* < MMC1 Clock enable */
0070 #define CKEN_MMC2   13  /* < MMC2 clock enable */
0071 #define CKEN_KEYPAD 14  /* < Keypand Controller Clock Enable */
0072 #define CKEN_CIR    15  /* < Consumer IR Clock Enable */
0073 #define CKEN_USIM0  17  /* < USIM[0] Clock Enable */
0074 #define CKEN_USIM1  18  /* < USIM[1] Clock Enable */
0075 #define CKEN_TPM    19  /* < TPM clock enable */
0076 #define CKEN_UDC    20  /* < UDC clock enable */
0077 #define CKEN_BTUART 21  /* < BTUART clock enable */
0078 #define CKEN_FFUART 22  /* < FFUART clock enable */
0079 #define CKEN_STUART 23  /* < STUART clock enable */
0080 #define CKEN_AC97   24  /* < AC97 clock enable */
0081 #define CKEN_TOUCH  25  /* < Touch screen Interface Clock Enable */
0082 #define CKEN_SSP1   26  /* < SSP1 clock enable */
0083 #define CKEN_SSP2   27  /* < SSP2 clock enable */
0084 #define CKEN_SSP3   28  /* < SSP3 clock enable */
0085 #define CKEN_SSP4   29  /* < SSP4 clock enable */
0086 #define CKEN_MSL0   30  /* < MSL0 clock enable */
0087 #define CKEN_PWM0   32  /* < PWM[0] clock enable */
0088 #define CKEN_PWM1   33  /* < PWM[1] clock enable */
0089 #define CKEN_I2C    36  /* < I2C clock enable */
0090 #define CKEN_INTC   38  /* < Interrupt controller clock enable */
0091 #define CKEN_GPIO   39  /* < GPIO clock enable */
0092 #define CKEN_1WIRE  40  /* < 1-wire clock enable */
0093 #define CKEN_HSIO2  41  /* < HSIO2 clock enable */
0094 #define CKEN_MINI_IM    48  /* < Mini-IM */
0095 #define CKEN_MINI_LCD   49  /* < Mini LCD */
0096
0097 #define CKEN_MMC3   5   /* < MMC3 Clock Enable */
0098 #define CKEN_MVED   43  /* < MVED clock enable */
0099
0100 /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
0101 #define CKEN_PXA300_GCU     42  /* Graphics controller clock enable */
0102 #define CKEN_PXA320_GCU     7   /* Graphics controller clock enable */
0103
0104
0105 enum {
0106     PXA_CORE_60Mhz = 0,
0107     PXA_CORE_RUN,
0108     PXA_CORE_TURBO,
0109 };
0110
0111 enum {
0112     PXA_BUS_60Mhz = 0,
0113     PXA_BUS_HSS,
0114 };
0115
0116 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
0117 static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
0118
0119 /* crystal frequency to static memory controller multiplier (SMCFS) */
0120 static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
0121 static const char * const get_freq_khz[] = {
0122     "core", "ring_osc_60mhz", "run", "cpll", "system_bus"
0123 };
0124
0125 static void __iomem *clk_regs;
0126
0127 /*
0128  * Get the clock frequency as reflected by ACSR and the turbo flag.
0129  * We assume these values have been applied via a fcs.
0130  * If info is not 0 we also display the current settings.
0131  */
0132 unsigned int pxa3xx_get_clk_frequency_khz(int info)
0133 {
0134     struct clk *clk;
0135     unsigned long clks[5];
0136     int i;
0137
0138     for (i = 0; i < 5; i++) {
0139         clk = clk_get(NULL, get_freq_khz[i]);
0140         if (IS_ERR(clk)) {
0141             clks[i] = 0;
0142         } else {
0143             clks[i] = clk_get_rate(clk);
0144             clk_put(clk);
0145         }
0146     }
0147     if (info) {
0148         pr_info("RO Mode clock: %ld.%02ldMHz\n",
0149             clks[1] / 1000000, (clks[0] % 1000000) / 10000);
0150         pr_info("Run Mode clock: %ld.%02ldMHz\n",
0151             clks[2] / 1000000, (clks[1] % 1000000) / 10000);
0152         pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
0153             clks[3] / 1000000, (clks[2] % 1000000) / 10000);
0154         pr_info("System bus clock: %ld.%02ldMHz\n",
0155             clks[4] / 1000000, (clks[4] % 1000000) / 10000);
0156     }
0157     return (unsigned int)clks[0] / KHz;
0158 }
0159
0160 void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 mask)
0161 {
0162     u32 accr = readl(clk_regs + ACCR);
0163
0164     accr &= ~disable;
0165     accr |= enable;
0166
0167     writel(accr, ACCR);
0168     if (xclkcfg)
0169         __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
0170
0171     while ((readl(clk_regs + ACSR) & mask) != (accr & mask))
0172         cpu_relax();
0173 }
0174
0175 static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw,
0176                          unsigned long parent_rate)
0177 {
0178     unsigned long ac97_div, rate;
0179
0180     ac97_div = readl(clk_regs + AC97_DIV);
0181
0182     /* This may loose precision for some rates but won't for the
0183      * standard 24.576MHz.
0184      */
0185     rate = parent_rate / 2;
0186     rate /= ((ac97_div >> 12) & 0x7fff);
0187     rate *= (ac97_div & 0xfff);
0188
0189     return rate;
0190 }
0191 PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" };
0192 RATE_RO_OPS(clk_pxa3xx_ac97, "ac97");
0193
0194 static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw,
0195                           unsigned long parent_rate)
0196 {
0197     unsigned long acsr = readl(clk_regs + ACSR);
0198
0199     return (parent_rate / 48)  * smcfs_mult[(acsr >> 23) & 0x7] /
0200         pxa3xx_smemc_get_memclkdiv();
0201
0202 }
0203 PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" };
0204 RATE_RO_OPS(clk_pxa3xx_smemc, "smemc");
0205
0206 static bool pxa3xx_is_ring_osc_forced(void)
0207 {
0208     unsigned long acsr = readl(clk_regs + ACSR);
0209
0210     return acsr & ACCR_D0CS;
0211 }
0212
0213 PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" };
0214 PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" };
0215 PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" };
0216 PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
0217 PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
0218 PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
0219
0220 #define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? CKENB : CKENA)
0221 #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp,  \
0222             div_hp, bit, is_lp, flags)              \
0223     PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp,     \
0224          mult_hp, div_hp, is_lp,  CKEN_AB(bit),         \
0225          (CKEN_ ## bit % 32), flags)
0226 #define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp,      \
0227              mult_hp, div_hp, delay)            \
0228     PXA3XX_CKEN(dev_id, con_id, pxa3xx_pbus_parents, mult_lp,   \
0229             div_lp, mult_hp, div_hp, bit, pxa3xx_is_ring_osc_forced, 0)
0230 #define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents)         \
0231     PXA_CKEN_1RATE(dev_id, con_id, bit, parents,            \
0232                CKEN_AB(bit), (CKEN_ ## bit % 32), 0)
0233
0234 static struct desc_clk_cken pxa3xx_clocks[] __initdata = {
0235     PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1),
0236     PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1),
0237     PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1),
0238     PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0),
0239     PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5),
0240     PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0),
0241     PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0),
0242     PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
0243     PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0),
0244     PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0),
0245     PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0),
0246     PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0),
0247
0248     PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
0249               pxa3xx_32Khz_bus_parents),
0250     PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents),
0251     PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents),
0252     PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents),
0253     PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents),
0254
0255     PXA3XX_CKEN(NULL, "AC97CLK", pxa3xx_ac97_bus_parents, 1, 4, 1, 1, AC97,
0256             pxa3xx_is_ring_osc_forced, 0),
0257     PXA3XX_CKEN(NULL, "CAMCLK", pxa3xx_sbus_parents, 1, 2, 1, 1, CAMERA,
0258             pxa3xx_is_ring_osc_forced, 0),
0259     PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD,
0260             pxa3xx_is_ring_osc_forced, 0),
0261     PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4,
0262             1, 1, SMC, pxa3xx_is_ring_osc_forced, CLK_IGNORE_UNUSED),
0263 };
0264
0265 static struct desc_clk_cken pxa300_310_clocks[] __initdata = {
0266
0267     PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
0268     PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
0269     PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
0270 };
0271
0272 static struct desc_clk_cken pxa320_clocks[] __initdata = {
0273     PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0),
0274     PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0),
0275     PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
0276 };
0277
0278 static struct desc_clk_cken pxa93x_clocks[] __initdata = {
0279
0280     PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
0281     PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
0282     PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
0283 };
0284
0285 static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw,
0286                         unsigned long parent_rate)
0287 {
0288     unsigned long acsr = readl(clk_regs + ACSR);
0289     unsigned int hss = (acsr >> 14) & 0x3;
0290
0291     if (pxa3xx_is_ring_osc_forced())
0292         return parent_rate;
0293     return parent_rate / 48 * hss_mult[hss];
0294 }
0295
0296 static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw)
0297 {
0298     if (pxa3xx_is_ring_osc_forced())
0299         return PXA_BUS_60Mhz;
0300     else
0301         return PXA_BUS_HSS;
0302 }
0303
0304 PARENTS(clk_pxa3xx_system_bus) = { "ring_osc_60mhz", "spll_624mhz" };
0305 MUX_RO_RATE_RO_OPS(clk_pxa3xx_system_bus, "system_bus");
0306
0307 static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw,
0308                           unsigned long parent_rate)
0309 {
0310     return parent_rate;
0311 }
0312
0313 static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw)
0314 {
0315     unsigned long xclkcfg;
0316     unsigned int t;
0317
0318     if (pxa3xx_is_ring_osc_forced())
0319         return PXA_CORE_60Mhz;
0320
0321     /* Read XCLKCFG register turbo bit */
0322     __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
0323     t = xclkcfg & 0x1;
0324
0325     if (t)
0326         return PXA_CORE_TURBO;
0327     return PXA_CORE_RUN;
0328 }
0329 PARENTS(clk_pxa3xx_core) = { "ring_osc_60mhz", "run", "cpll" };
0330 MUX_RO_RATE_RO_OPS(clk_pxa3xx_core, "core");
0331
0332 static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw,
0333                          unsigned long parent_rate)
0334 {
0335     unsigned long acsr = readl(clk_regs + ACSR);
0336     unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
0337     unsigned int t, xclkcfg;
0338
0339     /* Read XCLKCFG register turbo bit */
0340     __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
0341     t = xclkcfg & 0x1;
0342
0343     return t ? (parent_rate / xn) * 2 : parent_rate;
0344 }
0345 PARENTS(clk_pxa3xx_run) = { "cpll" };
0346 RATE_RO_OPS(clk_pxa3xx_run, "run");
0347
0348 static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw,
0349     unsigned long parent_rate)
0350 {
0351     unsigned long acsr = readl(clk_regs + ACSR);
0352     unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
0353     unsigned int xl = acsr & ACCR_XL_MASK;
0354     unsigned int t, xclkcfg;
0355
0356     /* Read XCLKCFG register turbo bit */
0357     __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
0358     t = xclkcfg & 0x1;
0359
0360     pr_info("RJK: parent_rate=%lu, xl=%u, xn=%u\n", parent_rate, xl, xn);
0361     return t ? parent_rate * xl * xn : parent_rate * xl;
0362 }
0363 PARENTS(clk_pxa3xx_cpll) = { "osc_13mhz" };
0364 RATE_RO_OPS(clk_pxa3xx_cpll, "cpll");
0365
0366 static void __init pxa3xx_register_core(void)
0367 {
0368     clk_register_clk_pxa3xx_cpll();
0369     clk_register_clk_pxa3xx_run();
0370
0371     clkdev_pxa_register(CLK_CORE, "core", NULL,
0372                 clk_register_clk_pxa3xx_core());
0373 }
0374
0375 static void __init pxa3xx_register_plls(void)
0376 {
0377     clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
0378                 CLK_GET_RATE_NOCACHE,
0379                 13 * MHz);
0380     clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
0381                 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
0382                             CLK_GET_RATE_NOCACHE,
0383                             32768));
0384     clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
0385                 CLK_GET_RATE_NOCACHE,
0386                 120 * MHz);
0387     clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
0388     clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1);
0389     clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz",
0390                   0, 1, 2);
0391 }
0392
0393 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
0394     { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
0395 struct dummy_clk {
0396     const char *con_id;
0397     const char *dev_id;
0398     const char *parent;
0399 };
0400 static struct dummy_clk dummy_clks[] __initdata = {
0401     DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"),
0402     DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
0403     DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
0404     DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"),
0405 };
0406
0407 static void __init pxa3xx_dummy_clocks_init(void)
0408 {
0409     struct clk *clk;
0410     struct dummy_clk *d;
0411     const char *name;
0412     int i;
0413
0414     for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
0415         d = &dummy_clks[i];
0416         name = d->dev_id ? d->dev_id : d->con_id;
0417         clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
0418         clk_register_clkdev(clk, d->con_id, d->dev_id);
0419     }
0420 }
0421
0422 static void __init pxa3xx_base_clocks_init(void __iomem *oscc_reg)
0423 {
0424     struct clk *clk;
0425
0426     pxa3xx_register_plls();
0427     pxa3xx_register_core();
0428     clk_register_clk_pxa3xx_system_bus();
0429     clk_register_clk_pxa3xx_ac97();
0430     clk_register_clk_pxa3xx_smemc();
0431     clk = clk_register_gate(NULL, "CLK_POUT",
0432                 "osc_13mhz", 0, oscc_reg, 11, 0, NULL);
0433     clk_register_clkdev(clk, "CLK_POUT", NULL);
0434     clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL,
0435                 clk_register_fixed_factor(NULL, "os-timer0",
0436                               "osc_13mhz", 0, 1, 4));
0437 }
0438
0439 int __init pxa3xx_clocks_init(void __iomem *regs, void __iomem *oscc_reg)
0440 {
0441     int ret;
0442
0443     clk_regs = regs;
0444     pxa3xx_base_clocks_init(oscc_reg);
0445     pxa3xx_dummy_clocks_init();
0446     ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks), regs);
0447     if (ret)
0448         return ret;
0449     if (cpu_is_pxa320())
0450         return clk_pxa_cken_init(pxa320_clocks,
0451                      ARRAY_SIZE(pxa320_clocks), regs);
0452     if (cpu_is_pxa300() || cpu_is_pxa310())
0453         return clk_pxa_cken_init(pxa300_310_clocks,
0454                      ARRAY_SIZE(pxa300_310_clocks), regs);
0455     return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks), regs);
0456 }
0457
0458 static void __init pxa3xx_dt_clocks_init(struct device_node *np)
0459 {
0460     pxa3xx_clocks_init(ioremap(0x41340000, 0x10), ioremap(0x41350000, 4));
0461     clk_pxa_dt_common_init(np);
0462 }
0463 CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);