clk/pxa/clk-pxa27x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Marvell PXA27x family clocks
0004  *
0005  * Copyright (C) 2014 Robert Jarzmik
0006  *
0007  * Heavily inspired from former arch/arm/mach-pxa/clock.c.
0008  */
0009 #include <linux/clk-provider.h>
0010 #include <linux/io.h>
0011 #include <linux/clk.h>
0012 #include <linux/clkdev.h>
0013 #include <linux/of.h>
0014 #include <linux/soc/pxa/smemc.h>
0015
0016 #include <dt-bindings/clock/pxa-clock.h>
0017 #include "clk-pxa.h"
0018 #include "clk-pxa2xx.h"
0019
0020 #define KHz 1000
0021 #define MHz (1000 * 1000)
0022
0023 enum {
0024     PXA_CORE_13Mhz = 0,
0025     PXA_CORE_RUN,
0026     PXA_CORE_TURBO,
0027 };
0028
0029 enum {
0030     PXA_BUS_13Mhz = 0,
0031     PXA_BUS_RUN,
0032 };
0033
0034 enum {
0035     PXA_LCD_13Mhz = 0,
0036     PXA_LCD_RUN,
0037 };
0038
0039 enum {
0040     PXA_MEM_13Mhz = 0,
0041     PXA_MEM_SYSTEM_BUS,
0042     PXA_MEM_RUN,
0043 };
0044
0045 #define PXA27x_CLKCFG(B, HT, T)         \
0046     (CLKCFG_FCS |               \
0047      ((B)  ? CLKCFG_FASTBUS : 0) |      \
0048      ((HT) ? CLKCFG_HALFTURBO : 0) |    \
0049      ((T)  ? CLKCFG_TURBO : 0))
0050 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
0051
0052 /* Define the refresh period in mSec for the SDRAM and the number of rows */
0053 #define SDRAM_TREF  64  /* standard 64ms SDRAM */
0054
0055 static void __iomem *clk_regs;
0056
0057 static const char * const get_freq_khz[] = {
0058     "core", "run", "cpll", "memory",
0059     "system_bus"
0060 };
0061
0062 static u32 mdrefr_dri(unsigned int freq_khz)
0063 {
0064     u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
0065
0066     return (interval - 31) / 32;
0067 }
0068
0069 /*
0070  * Get the clock frequency as reflected by CCSR and the turbo flag.
0071  * We assume these values have been applied via a fcs.
0072  * If info is not 0 we also display the current settings.
0073  */
0074 unsigned int pxa27x_get_clk_frequency_khz(int info)
0075 {
0076     struct clk *clk;
0077     unsigned long clks[5];
0078     int i;
0079
0080     for (i = 0; i < 5; i++) {
0081         clk = clk_get(NULL, get_freq_khz[i]);
0082         if (IS_ERR(clk)) {
0083             clks[i] = 0;
0084         } else {
0085             clks[i] = clk_get_rate(clk);
0086             clk_put(clk);
0087         }
0088     }
0089     if (info) {
0090         pr_info("Run Mode clock: %ld.%02ldMHz\n",
0091             clks[1] / 1000000, (clks[1] % 1000000) / 10000);
0092         pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
0093             clks[2] / 1000000, (clks[2] % 1000000) / 10000);
0094         pr_info("Memory clock: %ld.%02ldMHz\n",
0095             clks[3] / 1000000, (clks[3] % 1000000) / 10000);
0096         pr_info("System bus clock: %ld.%02ldMHz\n",
0097             clks[4] / 1000000, (clks[4] % 1000000) / 10000);
0098     }
0099     return (unsigned int)clks[0] / KHz;
0100 }
0101
0102 bool pxa27x_is_ppll_disabled(void)
0103 {
0104     unsigned long ccsr = readl(clk_regs + CCSR);
0105
0106     return ccsr & (1 << CCCR_PPDIS_BIT);
0107 }
0108
0109 #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp,       \
0110             bit, is_lp, flags)                  \
0111     PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp,   \
0112          is_lp,  CKEN, CKEN_ ## bit, flags)
0113 #define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)   \
0114     PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp,   \
0115             div_hp, bit, pxa27x_is_ppll_disabled, 0)
0116
0117 PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
0118 PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
0119 PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
0120 PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
0121 PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
0122
0123 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)      \
0124     PXA_CKEN_1RATE(dev_id, con_id, bit, parents,            \
0125                CKEN, CKEN_ ## bit, 0)
0126 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)   \
0127     PXA_CKEN_1RATE(dev_id, con_id, bit, parents,            \
0128                CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
0129
0130 static struct desc_clk_cken pxa27x_clocks[] __initdata = {
0131     PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
0132     PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
0133     PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
0134     PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
0135     PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
0136     PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
0137     PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
0138     PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
0139     PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
0140     PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
0141     PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
0142     PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
0143     PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
0144     PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
0145     PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
0146     PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
0147     PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
0148     PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
0149     PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
0150     PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
0151     PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
0152
0153     PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
0154               pxa27x_32Mhz_bus_parents, 0),
0155     PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
0156     PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
0157     PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
0158               pxa27x_lcd_bus_parents, 0),
0159     PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
0160                  pxa27x_membus_parents, 0),
0161
0162 };
0163
0164 /*
0165  * PXA270 definitions
0166  *
0167  * For the PXA27x:
0168  * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
0169  *
0170  * A = 0 => memory controller clock from table 3-7,
0171  * A = 1 => memory controller clock = system bus clock
0172  * Run mode frequency   = 13 MHz * L
0173  * Turbo mode frequency = 13 MHz * L * N
0174  * System bus frequency = 13 MHz * L / (B + 1)
0175  *
0176  * In CCCR:
0177  * A = 1
0178  * L = 16     oscillator to run mode ratio
0179  * 2N = 6     2 * (turbo mode to run mode ratio)
0180  *
0181  * In CCLKCFG:
0182  * B = 1      Fast bus mode
0183  * HT = 0     Half-Turbo mode
0184  * T = 1      Turbo mode
0185  *
0186  * For now, just support some of the combinations in table 3-7 of
0187  * PXA27x Processor Family Developer's Manual to simplify frequency
0188  * change sequences.
0189  */
0190 static struct pxa2xx_freq pxa27x_freqs[] = {
0191     {104000000, 104000, PXA27x_CCCR(1,  8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
0192     {156000000, 104000, PXA27x_CCCR(1,  8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
0193     {208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
0194     {312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
0195     {416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
0196     {520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
0197     {624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
0198 };
0199
0200 static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
0201     unsigned long parent_rate)
0202 {
0203     unsigned long clkcfg;
0204     unsigned int t, ht;
0205     unsigned int l, L, n2, N;
0206     unsigned long ccsr = readl(clk_regs + CCSR);
0207
0208     asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
0209     t  = clkcfg & (1 << 0);
0210     ht = clkcfg & (1 << 2);
0211
0212     l  = ccsr & CCSR_L_MASK;
0213     n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
0214     L  = l * parent_rate;
0215     N  = (L * n2) / 2;
0216
0217     return N;
0218 }
0219
0220 static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
0221                       struct clk_rate_request *req)
0222 {
0223     return pxa2xx_determine_rate(req, pxa27x_freqs,
0224                      ARRAY_SIZE(pxa27x_freqs));
0225 }
0226
0227 static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
0228                     unsigned long parent_rate)
0229 {
0230     int i;
0231
0232     pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
0233     for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
0234         if (pxa27x_freqs[i].cpll == rate)
0235             break;
0236
0237     if (i >= ARRAY_SIZE(pxa27x_freqs))
0238         return -EINVAL;
0239
0240     pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR);
0241     return 0;
0242 }
0243
0244 PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
0245 RATE_OPS(clk_pxa27x_cpll, "cpll");
0246
0247 static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
0248                           unsigned long parent_rate)
0249 {
0250     unsigned int l, osc_forced;
0251     unsigned long ccsr = readl(clk_regs + CCSR);
0252     unsigned long cccr = readl(clk_regs + CCCR);
0253
0254     l  = ccsr & CCSR_L_MASK;
0255     osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
0256     if (osc_forced) {
0257         if (cccr & (1 << CCCR_LCD_26_BIT))
0258             return parent_rate * 2;
0259         else
0260             return parent_rate;
0261     }
0262
0263     if (l <= 7)
0264         return parent_rate;
0265     if (l <= 16)
0266         return parent_rate / 2;
0267     return parent_rate / 4;
0268 }
0269
0270 static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
0271 {
0272     unsigned int osc_forced;
0273     unsigned long ccsr = readl(clk_regs + CCSR);
0274
0275     osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
0276     if (osc_forced)
0277         return PXA_LCD_13Mhz;
0278     else
0279         return PXA_LCD_RUN;
0280 }
0281
0282 PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
0283 MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
0284
0285 static void __init pxa27x_register_plls(void)
0286 {
0287     clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
0288                 CLK_GET_RATE_NOCACHE,
0289                 13 * MHz);
0290     clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
0291                 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
0292                             CLK_GET_RATE_NOCACHE,
0293                             32768 * KHz));
0294     clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
0295     clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
0296 }
0297
0298 static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
0299 {
0300     unsigned long clkcfg;
0301     unsigned int t, ht, osc_forced;
0302     unsigned long ccsr = readl(clk_regs + CCSR);
0303
0304     osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
0305     if (osc_forced)
0306         return PXA_CORE_13Mhz;
0307
0308     asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
0309     t  = clkcfg & (1 << 0);
0310     ht = clkcfg & (1 << 2);
0311
0312     if (ht || t)
0313         return PXA_CORE_TURBO;
0314     return PXA_CORE_RUN;
0315 }
0316
0317 static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
0318 {
0319     if (index > PXA_CORE_TURBO)
0320         return -EINVAL;
0321
0322     pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
0323
0324     return 0;
0325 }
0326
0327 static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
0328                       struct clk_rate_request *req)
0329 {
0330     return __clk_mux_determine_rate(hw, req);
0331 }
0332
0333 PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
0334 MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
0335
0336 static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
0337                          unsigned long parent_rate)
0338 {
0339     unsigned long ccsr = readl(clk_regs + CCSR);
0340     unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
0341
0342     return (parent_rate / n2) * 2;
0343 }
0344 PARENTS(clk_pxa27x_run) = { "cpll" };
0345 RATE_RO_OPS(clk_pxa27x_run, "run");
0346
0347 static void __init pxa27x_register_core(void)
0348 {
0349     clkdev_pxa_register(CLK_NONE, "cpll", NULL,
0350                 clk_register_clk_pxa27x_cpll());
0351     clkdev_pxa_register(CLK_NONE, "run", NULL,
0352                 clk_register_clk_pxa27x_run());
0353     clkdev_pxa_register(CLK_CORE, "core", NULL,
0354                 clk_register_clk_pxa27x_core());
0355 }
0356
0357 static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
0358                             unsigned long parent_rate)
0359 {
0360     unsigned long clkcfg;
0361     unsigned int b, osc_forced;
0362     unsigned long ccsr = readl(clk_regs + CCSR);
0363
0364     osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
0365     asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
0366     b  = clkcfg & (1 << 3);
0367
0368     if (osc_forced)
0369         return parent_rate;
0370     if (b)
0371         return parent_rate;
0372     else
0373         return parent_rate / 2;
0374 }
0375
0376 static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
0377 {
0378     unsigned int osc_forced;
0379     unsigned long ccsr = readl(clk_regs + CCSR);
0380
0381     osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
0382     if (osc_forced)
0383         return PXA_BUS_13Mhz;
0384     else
0385         return PXA_BUS_RUN;
0386 }
0387
0388 PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
0389 MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
0390
0391 static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
0392                         unsigned long parent_rate)
0393 {
0394     unsigned int a, l, osc_forced;
0395     unsigned long cccr = readl(clk_regs + CCCR);
0396     unsigned long ccsr = readl(clk_regs + CCSR);
0397
0398     osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
0399     a = cccr & (1 << CCCR_A_BIT);
0400     l  = ccsr & CCSR_L_MASK;
0401
0402     if (osc_forced || a)
0403         return parent_rate;
0404     if (l <= 10)
0405         return parent_rate;
0406     if (l <= 20)
0407         return parent_rate / 2;
0408     return parent_rate / 4;
0409 }
0410
0411 static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
0412 {
0413     unsigned int osc_forced, a;
0414     unsigned long cccr = readl(clk_regs + CCCR);
0415     unsigned long ccsr = readl(clk_regs + CCSR);
0416
0417     osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
0418     a = cccr & (1 << CCCR_A_BIT);
0419     if (osc_forced)
0420         return PXA_MEM_13Mhz;
0421     if (a)
0422         return PXA_MEM_SYSTEM_BUS;
0423     else
0424         return PXA_MEM_RUN;
0425 }
0426
0427 PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
0428 MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
0429
0430 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
0431     { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
0432 struct dummy_clk {
0433     const char *con_id;
0434     const char *dev_id;
0435     const char *parent;
0436 };
0437 static struct dummy_clk dummy_clks[] __initdata = {
0438     DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
0439     DUMMY_CLK(NULL, "pxa-rtc", "osc_32_768khz"),
0440     DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
0441     DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
0442 };
0443
0444 static void __init pxa27x_dummy_clocks_init(void)
0445 {
0446     struct clk *clk;
0447     struct dummy_clk *d;
0448     const char *name;
0449     int i;
0450
0451     for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
0452         d = &dummy_clks[i];
0453         name = d->dev_id ? d->dev_id : d->con_id;
0454         clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
0455         clk_register_clkdev(clk, d->con_id, d->dev_id);
0456     }
0457 }
0458
0459 static void __init pxa27x_base_clocks_init(void)
0460 {
0461     pxa27x_register_plls();
0462     pxa27x_register_core();
0463     clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
0464                 clk_register_clk_pxa27x_system_bus());
0465     clkdev_pxa_register(CLK_NONE, "memory", NULL,
0466                 clk_register_clk_pxa27x_memory());
0467     clk_register_clk_pxa27x_lcd_base();
0468 }
0469
0470 int __init pxa27x_clocks_init(void __iomem *regs)
0471 {
0472     clk_regs = regs;
0473     pxa27x_base_clocks_init();
0474     pxa27x_dummy_clocks_init();
0475     return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks), regs);
0476 }
0477
0478 static void __init pxa27x_dt_clocks_init(struct device_node *np)
0479 {
0480     pxa27x_clocks_init(ioremap(0x41300000ul, 0x10));
0481     clk_pxa_dt_common_init(np);
0482 }
0483 CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);