clk/pxa/clk-pxa25x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Marvell PXA25x family clocks
0004  *
0005  * Copyright (C) 2014 Robert Jarzmik
0006  *
0007  * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
0008  *
0009  * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
0010  * should go away.
0011  */
0012 #include <linux/clk-provider.h>
0013 #include <linux/clk.h>
0014 #include <linux/clkdev.h>
0015 #include <linux/io.h>
0016 #include <linux/of.h>
0017 #include <linux/soc/pxa/smemc.h>
0018
0019 #include <dt-bindings/clock/pxa-clock.h>
0020 #include "clk-pxa.h"
0021 #include "clk-pxa2xx.h"
0022
0023 #define KHz 1000
0024 #define MHz (1000 * 1000)
0025
0026 enum {
0027     PXA_CORE_RUN = 0,
0028     PXA_CORE_TURBO,
0029 };
0030
0031 #define PXA25x_CLKCFG(T)            \
0032     (CLKCFG_FCS |               \
0033      ((T) ? CLKCFG_TURBO : 0))
0034 #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
0035
0036 /* Define the refresh period in mSec for the SDRAM and the number of rows */
0037 #define SDRAM_TREF  64  /* standard 64ms SDRAM */
0038
0039 /*
0040  * Various clock factors driven by the CCCR register.
0041  */
0042 static void __iomem *clk_regs;
0043
0044 /* Crystal Frequency to Memory Frequency Multiplier (L) */
0045 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
0046
0047 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
0048 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
0049
0050 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
0051 /* Note: we store the value N * 2 here. */
0052 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
0053
0054 static const char * const get_freq_khz[] = {
0055     "core", "run", "cpll", "memory"
0056 };
0057
0058 static u32 mdrefr_dri(unsigned int freq_khz)
0059 {
0060     u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
0061
0062     return interval / 32;
0063 }
0064
0065 /*
0066  * Get the clock frequency as reflected by CCCR and the turbo flag.
0067  * We assume these values have been applied via a fcs.
0068  * If info is not 0 we also display the current settings.
0069  */
0070 unsigned int pxa25x_get_clk_frequency_khz(int info)
0071 {
0072     struct clk *clk;
0073     unsigned long clks[5];
0074     int i;
0075
0076     for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
0077         clk = clk_get(NULL, get_freq_khz[i]);
0078         if (IS_ERR(clk)) {
0079             clks[i] = 0;
0080         } else {
0081             clks[i] = clk_get_rate(clk);
0082             clk_put(clk);
0083         }
0084     }
0085
0086     if (info) {
0087         pr_info("Run Mode clock: %ld.%02ldMHz\n",
0088             clks[1] / 1000000, (clks[1] % 1000000) / 10000);
0089         pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
0090             clks[2] / 1000000, (clks[2] % 1000000) / 10000);
0091         pr_info("Memory clock: %ld.%02ldMHz\n",
0092             clks[3] / 1000000, (clks[3] % 1000000) / 10000);
0093     }
0094
0095     return (unsigned int)clks[0] / KHz;
0096 }
0097
0098 static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
0099                         unsigned long parent_rate)
0100 {
0101     unsigned long cccr = readl(clk_regs + CCCR);
0102     unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
0103
0104     return parent_rate / m;
0105 }
0106 PARENTS(clk_pxa25x_memory) = { "run" };
0107 RATE_RO_OPS(clk_pxa25x_memory, "memory");
0108
0109 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
0110 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
0111 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
0112
0113 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div,         \
0114             bit, is_lp, flags)                  \
0115     PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div,    \
0116          is_lp,  CKEN, CKEN_ ## bit, flags)
0117 #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
0118     PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
0119             div_hp, bit, NULL, 0)
0120 #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
0121     PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp,    \
0122             div_hp, bit, NULL, 0)
0123 #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)   \
0124     PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp,   \
0125             div_hp, bit, NULL, 0)
0126
0127 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)      \
0128     PXA_CKEN_1RATE(dev_id, con_id, bit, parents,            \
0129                CKEN, CKEN_ ## bit, 0)
0130 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)   \
0131     PXA_CKEN_1RATE(dev_id, con_id, bit, parents,            \
0132                CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
0133
0134 static struct desc_clk_cken pxa25x_clocks[] __initdata = {
0135     PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
0136     PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
0137     PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
0138     PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
0139     PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
0140     PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
0141     PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
0142     PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
0143     PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
0144     PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
0145     PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
0146     PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
0147     PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
0148     PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
0149     PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
0150
0151     PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
0152     PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
0153                  clk_pxa25x_memory_parents, 0),
0154 };
0155
0156 /*
0157  * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
0158  *   - freq_cpll = n * m * L * 3.6864 MHz
0159  *   - n = N2 / 2
0160  *   - m = 2^(M - 1), where 1 <= M <= 3
0161  *   - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
0162  */
0163 static struct pxa2xx_freq pxa25x_freqs[] = {
0164     /* CPU  MEMBUS  CCCR                  DIV2 CCLKCFG      */
0165     { 99532800, 99500, PXA25x_CCCR(2,  1, 1),  1, PXA25x_CLKCFG(1)},
0166     {199065600, 99500, PXA25x_CCCR(4,  1, 1),  0, PXA25x_CLKCFG(1)},
0167     {298598400, 99500, PXA25x_CCCR(3,  2, 1),  0, PXA25x_CLKCFG(1)},
0168     {398131200, 99500, PXA25x_CCCR(4,  2, 1),  0, PXA25x_CLKCFG(1)},
0169 };
0170
0171 static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
0172 {
0173     unsigned long clkcfg;
0174     unsigned int t;
0175
0176     asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
0177     t  = clkcfg & (1 << 0);
0178     if (t)
0179         return PXA_CORE_TURBO;
0180     return PXA_CORE_RUN;
0181 }
0182
0183 static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
0184 {
0185     if (index > PXA_CORE_TURBO)
0186         return -EINVAL;
0187
0188     pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
0189
0190     return 0;
0191 }
0192
0193 static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
0194                       struct clk_rate_request *req)
0195 {
0196     return __clk_mux_determine_rate(hw, req);
0197 }
0198
0199 PARENTS(clk_pxa25x_core) = { "run", "cpll" };
0200 MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
0201
0202 static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
0203                          unsigned long parent_rate)
0204 {
0205     unsigned long cccr = readl(clk_regs + CCCR);
0206     unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
0207
0208     return (parent_rate / n2) * 2;
0209 }
0210 PARENTS(clk_pxa25x_run) = { "cpll" };
0211 RATE_RO_OPS(clk_pxa25x_run, "run");
0212
0213 static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
0214     unsigned long parent_rate)
0215 {
0216     unsigned long clkcfg, cccr = readl(clk_regs + CCCR);
0217     unsigned int l, m, n2, t;
0218
0219     asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
0220     t = clkcfg & (1 << 0);
0221     l  =  L_clk_mult[(cccr >> 0) & 0x1f];
0222     m = M_clk_mult[(cccr >> 5) & 0x03];
0223     n2 = N2_clk_mult[(cccr >> 7) & 0x07];
0224
0225     return m * l * n2 * parent_rate / 2;
0226 }
0227
0228 static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
0229                       struct clk_rate_request *req)
0230 {
0231     return pxa2xx_determine_rate(req, pxa25x_freqs,
0232                      ARRAY_SIZE(pxa25x_freqs));
0233 }
0234
0235 static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
0236                     unsigned long parent_rate)
0237 {
0238     int i;
0239
0240     pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
0241     for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
0242         if (pxa25x_freqs[i].cpll == rate)
0243             break;
0244
0245     if (i >= ARRAY_SIZE(pxa25x_freqs))
0246         return -EINVAL;
0247
0248     pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR);
0249
0250     return 0;
0251 }
0252 PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
0253 RATE_OPS(clk_pxa25x_cpll, "cpll");
0254
0255 static void __init pxa25x_register_core(void)
0256 {
0257     clkdev_pxa_register(CLK_NONE, "cpll", NULL,
0258                 clk_register_clk_pxa25x_cpll());
0259     clkdev_pxa_register(CLK_NONE, "run", NULL,
0260                 clk_register_clk_pxa25x_run());
0261     clkdev_pxa_register(CLK_CORE, "core", NULL,
0262                 clk_register_clk_pxa25x_core());
0263 }
0264
0265 static void __init pxa25x_register_plls(void)
0266 {
0267     clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
0268                 CLK_GET_RATE_NOCACHE, 3686400);
0269     clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
0270                 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
0271                             CLK_GET_RATE_NOCACHE,
0272                             32768));
0273     clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
0274     clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
0275                   0, 26, 1);
0276     clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
0277                   0, 40, 1);
0278 }
0279
0280 static void __init pxa25x_base_clocks_init(void)
0281 {
0282     pxa25x_register_plls();
0283     pxa25x_register_core();
0284     clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
0285                 clk_register_clk_pxa25x_memory());
0286 }
0287
0288 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
0289     { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
0290 struct dummy_clk {
0291     const char *con_id;
0292     const char *dev_id;
0293     const char *parent;
0294 };
0295 static struct dummy_clk dummy_clks[] __initdata = {
0296     DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
0297     DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
0298     DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
0299     DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
0300     DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
0301     DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
0302     DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
0303 };
0304
0305 static void __init pxa25x_dummy_clocks_init(void)
0306 {
0307     struct clk *clk;
0308     struct dummy_clk *d;
0309     const char *name;
0310     int i;
0311
0312     /*
0313      * All pinctrl logic has been wiped out of the clock driver, especially
0314      * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
0315      * control (ie. pxa2xx_mfp_config() invocation).
0316      */
0317     for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
0318         d = &dummy_clks[i];
0319         name = d->dev_id ? d->dev_id : d->con_id;
0320         clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
0321         clk_register_clkdev(clk, d->con_id, d->dev_id);
0322     }
0323 }
0324
0325 int __init pxa25x_clocks_init(void __iomem *regs)
0326 {
0327     clk_regs = regs;
0328     pxa25x_base_clocks_init();
0329     pxa25x_dummy_clocks_init();
0330     return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs);
0331 }
0332
0333 static void __init pxa25x_dt_clocks_init(struct device_node *np)
0334 {
0335     pxa25x_clocks_init(ioremap(0x41300000ul, 0x10));
0336     clk_pxa_dt_common_init(np);
0337 }
0338 CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
0339            pxa25x_dt_clocks_init);