clk/pxa/clk-pxa.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Marvell PXA family clocks
0004  *
0005  * Copyright (C) 2014 Robert Jarzmik
0006  *
0007  * Common clock code for PXA clocks ("CKEN" type clocks + DT)
0008  */
0009 #ifndef _CLK_PXA_
0010 #define _CLK_PXA_
0011
0012 #define CLKCFG_TURBO        0x1
0013 #define CLKCFG_FCS      0x2
0014 #define CLKCFG_HALFTURBO    0x4
0015 #define CLKCFG_FASTBUS      0x8
0016
0017 #define PARENTS(name) \
0018     static const char *const name ## _parents[] __initconst
0019 #define MUX_RO_RATE_RO_OPS(name, clk_name)          \
0020     static struct clk_hw name ## _mux_hw;           \
0021     static struct clk_hw name ## _rate_hw;          \
0022     static const struct clk_ops name ## _mux_ops = {    \
0023         .get_parent = name ## _get_parent,      \
0024         .set_parent = dummy_clk_set_parent,     \
0025     };                          \
0026     static const struct clk_ops name ## _rate_ops = {   \
0027         .recalc_rate = name ## _get_rate,       \
0028     };                          \
0029     static struct clk * __init clk_register_ ## name(void)  \
0030     {                           \
0031         return clk_register_composite(NULL, clk_name,   \
0032             name ## _parents,           \
0033             ARRAY_SIZE(name ## _parents),       \
0034             &name ## _mux_hw, &name ## _mux_ops,    \
0035             &name ## _rate_hw, &name ## _rate_ops,  \
0036             NULL, NULL, CLK_GET_RATE_NOCACHE);  \
0037     }
0038
0039 #define RATE_RO_OPS(name, clk_name)             \
0040     static struct clk_hw name ## _rate_hw;          \
0041     static const struct clk_ops name ## _rate_ops = {   \
0042         .recalc_rate = name ## _get_rate,       \
0043     };                          \
0044     static struct clk * __init clk_register_ ## name(void)  \
0045     {                           \
0046         return clk_register_composite(NULL, clk_name,   \
0047             name ## _parents,           \
0048             ARRAY_SIZE(name ## _parents),       \
0049             NULL, NULL,             \
0050             &name ## _rate_hw, &name ## _rate_ops,  \
0051             NULL, NULL, CLK_GET_RATE_NOCACHE);  \
0052     }
0053
0054 #define RATE_OPS(name, clk_name)                \
0055     static struct clk_hw name ## _rate_hw;          \
0056     static const struct clk_ops name ## _rate_ops = {   \
0057         .recalc_rate = name ## _get_rate,       \
0058         .set_rate = name ## _set_rate,          \
0059         .determine_rate = name ## _determine_rate,  \
0060     };                          \
0061     static struct clk * __init clk_register_ ## name(void)  \
0062     {                           \
0063         return clk_register_composite(NULL, clk_name,   \
0064             name ## _parents,           \
0065             ARRAY_SIZE(name ## _parents),       \
0066             NULL, NULL,             \
0067             &name ## _rate_hw, &name ## _rate_ops,  \
0068             NULL, NULL, CLK_GET_RATE_NOCACHE);  \
0069     }
0070
0071 #define MUX_OPS(name, clk_name, flags)              \
0072     static struct clk_hw name ## _mux_hw;           \
0073     static const struct clk_ops name ## _mux_ops = {    \
0074         .get_parent = name ## _get_parent,      \
0075         .set_parent = name ## _set_parent,      \
0076         .determine_rate = name ## _determine_rate,  \
0077     };                          \
0078     static struct clk * __init clk_register_ ## name(void)  \
0079     {                           \
0080         return clk_register_composite(NULL, clk_name,   \
0081             name ## _parents,           \
0082             ARRAY_SIZE(name ## _parents),       \
0083             &name ## _mux_hw, &name ## _mux_ops,    \
0084             NULL, NULL,             \
0085             NULL, NULL,             \
0086             CLK_GET_RATE_NOCACHE | flags); \
0087     }
0088
0089 /*
0090  * CKEN clock type
0091  * This clock takes it source from 2 possible parents :
0092  *  - a low power parent
0093  *  - a normal parent
0094  *
0095  *  +------------+     +-----------+
0096  *  |  Low Power | --- | x mult_lp |
0097  *  |    Clock   |     | / div_lp  |\
0098  *  +------------+     +-----------+ \+-----+   +-----------+
0099  *                                    | Mux |---| CKEN gate |
0100  *  +------------+     +-----------+ /+-----+   +-----------+
0101  *  | High Power |     | x mult_hp |/
0102  *  |    Clock   | --- | / div_hp  |
0103  *  +------------+     +-----------+
0104  */
0105 struct desc_clk_cken {
0106     struct clk_hw hw;
0107     int ckid;
0108     int cken_reg;
0109     const char *name;
0110     const char *dev_id;
0111     const char *con_id;
0112     const char * const *parent_names;
0113     struct clk_fixed_factor lp;
0114     struct clk_fixed_factor hp;
0115     struct clk_gate gate;
0116     bool (*is_in_low_power)(void);
0117     const unsigned long flags;
0118 };
0119
0120 #define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp,   \
0121          _mult_hp, _div_hp, is_lp, _cken_reg, _cken_bit, flag)  \
0122     { .ckid = CLK_ ## _name, .name = #_name,            \
0123       .cken_reg = _cken_reg,                    \
0124       .dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\
0125       .lp = { .mult = _mult_lp, .div = _div_lp },           \
0126       .hp = { .mult = _mult_hp, .div = _div_hp },           \
0127       .is_in_low_power = is_lp,                 \
0128       .gate = { .bit_idx = _cken_bit }, \
0129       .flags = flag,                        \
0130     }
0131 #define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg,     \
0132                 cken_bit, flag)             \
0133     PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1,     \
0134          NULL, cken_reg, cken_bit, flag)
0135
0136 struct pxa2xx_freq {
0137     unsigned long cpll;
0138     unsigned int membus_khz;
0139     unsigned int cccr;
0140     unsigned int div2;
0141     unsigned int clkcfg;
0142 };
0143
0144 static inline int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
0145 {
0146     return 0;
0147 }
0148
0149 extern void clkdev_pxa_register(int ckid, const char *con_id,
0150                 const char *dev_id, struct clk *clk);
0151 extern int clk_pxa_cken_init(const struct desc_clk_cken *clks,
0152                  int nb_clks, void __iomem *clk_regs);
0153 void clk_pxa_dt_common_init(struct device_node *np);
0154
0155 void pxa2xx_core_turbo_switch(bool on);
0156 void pxa2xx_cpll_change(struct pxa2xx_freq *freq,
0157             u32 (*mdrefr_dri)(unsigned int),
0158             void __iomem *cccr);
0159 int pxa2xx_determine_rate(struct clk_rate_request *req,
0160               struct pxa2xx_freq *freqs,  int nb_freqs);
0161
0162 #endif