clk/pxa/clk-pxa.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Marvell PXA family clocks
0004  *
0005  * Copyright (C) 2014 Robert Jarzmik
0006  *
0007  * Common clock code for PXA clocks ("CKEN" type clocks + DT)
0008  */
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/clkdev.h>
0012 #include <linux/io.h>
0013 #include <linux/of.h>
0014 #include <linux/soc/pxa/smemc.h>
0015
0016 #include <dt-bindings/clock/pxa-clock.h>
0017 #include "clk-pxa.h"
0018
0019 #define KHz 1000
0020 #define MHz (1000 * 1000)
0021
0022 #define MDREFR_K0DB4    (1 << 29)   /* SDCLK0 Divide by 4 Control/Status */
0023 #define MDREFR_K2FREE   (1 << 25)   /* SDRAM Free-Running Control */
0024 #define MDREFR_K1FREE   (1 << 24)   /* SDRAM Free-Running Control */
0025 #define MDREFR_K0FREE   (1 << 23)   /* SDRAM Free-Running Control */
0026 #define MDREFR_SLFRSH   (1 << 22)   /* SDRAM Self-Refresh Control/Status */
0027 #define MDREFR_APD  (1 << 20)   /* SDRAM/SSRAM Auto-Power-Down Enable */
0028 #define MDREFR_K2DB2    (1 << 19)   /* SDCLK2 Divide by 2 Control/Status */
0029 #define MDREFR_K2RUN    (1 << 18)   /* SDCLK2 Run Control/Status */
0030 #define MDREFR_K1DB2    (1 << 17)   /* SDCLK1 Divide by 2 Control/Status */
0031 #define MDREFR_K1RUN    (1 << 16)   /* SDCLK1 Run Control/Status */
0032 #define MDREFR_E1PIN    (1 << 15)   /* SDCKE1 Level Control/Status */
0033 #define MDREFR_K0DB2    (1 << 14)   /* SDCLK0 Divide by 2 Control/Status */
0034 #define MDREFR_K0RUN    (1 << 13)   /* SDCLK0 Run Control/Status */
0035 #define MDREFR_E0PIN    (1 << 12)   /* SDCKE0 Level Control/Status */
0036 #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
0037 #define MDREFR_DRI_MASK 0xFFF
0038
0039 static DEFINE_SPINLOCK(pxa_clk_lock);
0040
0041 static struct clk *pxa_clocks[CLK_MAX];
0042 static struct clk_onecell_data onecell_data = {
0043     .clks = pxa_clocks,
0044     .clk_num = CLK_MAX,
0045 };
0046
0047 struct pxa_clk {
0048     struct clk_hw hw;
0049     struct clk_fixed_factor lp;
0050     struct clk_fixed_factor hp;
0051     struct clk_gate gate;
0052     bool (*is_in_low_power)(void);
0053 };
0054
0055 #define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
0056
0057 static unsigned long cken_recalc_rate(struct clk_hw *hw,
0058                       unsigned long parent_rate)
0059 {
0060     struct pxa_clk *pclk = to_pxa_clk(hw);
0061     struct clk_fixed_factor *fix;
0062
0063     if (!pclk->is_in_low_power || pclk->is_in_low_power())
0064         fix = &pclk->lp;
0065     else
0066         fix = &pclk->hp;
0067     __clk_hw_set_clk(&fix->hw, hw);
0068     return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);
0069 }
0070
0071 static const struct clk_ops cken_rate_ops = {
0072     .recalc_rate = cken_recalc_rate,
0073 };
0074
0075 static u8 cken_get_parent(struct clk_hw *hw)
0076 {
0077     struct pxa_clk *pclk = to_pxa_clk(hw);
0078
0079     if (!pclk->is_in_low_power)
0080         return 0;
0081     return pclk->is_in_low_power() ? 0 : 1;
0082 }
0083
0084 static const struct clk_ops cken_mux_ops = {
0085     .get_parent = cken_get_parent,
0086     .set_parent = dummy_clk_set_parent,
0087 };
0088
0089 void __init clkdev_pxa_register(int ckid, const char *con_id,
0090                 const char *dev_id, struct clk *clk)
0091 {
0092     if (!IS_ERR(clk) && (ckid != CLK_NONE))
0093         pxa_clocks[ckid] = clk;
0094     if (!IS_ERR(clk))
0095         clk_register_clkdev(clk, con_id, dev_id);
0096 }
0097
0098 int __init clk_pxa_cken_init(const struct desc_clk_cken *clks,
0099                  int nb_clks, void __iomem *clk_regs)
0100 {
0101     int i;
0102     struct pxa_clk *pxa_clk;
0103     struct clk *clk;
0104
0105     for (i = 0; i < nb_clks; i++) {
0106         pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
0107         pxa_clk->is_in_low_power = clks[i].is_in_low_power;
0108         pxa_clk->lp = clks[i].lp;
0109         pxa_clk->hp = clks[i].hp;
0110         pxa_clk->gate = clks[i].gate;
0111         pxa_clk->gate.reg = clk_regs + clks[i].cken_reg;
0112         pxa_clk->gate.lock = &pxa_clk_lock;
0113         clk = clk_register_composite(NULL, clks[i].name,
0114                          clks[i].parent_names, 2,
0115                          &pxa_clk->hw, &cken_mux_ops,
0116                          &pxa_clk->hw, &cken_rate_ops,
0117                          &pxa_clk->gate.hw, &clk_gate_ops,
0118                          clks[i].flags);
0119         clkdev_pxa_register(clks[i].ckid, clks[i].con_id,
0120                     clks[i].dev_id, clk);
0121     }
0122     return 0;
0123 }
0124
0125 void __init clk_pxa_dt_common_init(struct device_node *np)
0126 {
0127     of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
0128 }
0129
0130 void pxa2xx_core_turbo_switch(bool on)
0131 {
0132     unsigned long flags;
0133     unsigned int unused, clkcfg;
0134
0135     local_irq_save(flags);
0136
0137     asm("mrc p14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
0138     clkcfg &= ~CLKCFG_TURBO & ~CLKCFG_HALFTURBO;
0139     if (on)
0140         clkcfg |= CLKCFG_TURBO;
0141     clkcfg |= CLKCFG_FCS;
0142
0143     asm volatile(
0144     "   b   2f\n"
0145     "   .align  5\n"
0146     "1: mcr p14, 0, %1, c6, c0, 0\n"
0147     "   b   3f\n"
0148     "2: b   1b\n"
0149     "3: nop\n"
0150         : "=&r" (unused) : "r" (clkcfg));
0151
0152     local_irq_restore(flags);
0153 }
0154
0155 void pxa2xx_cpll_change(struct pxa2xx_freq *freq,
0156             u32 (*mdrefr_dri)(unsigned int),
0157             void __iomem *cccr)
0158 {
0159     unsigned int clkcfg = freq->clkcfg;
0160     unsigned int unused, preset_mdrefr, postset_mdrefr;
0161     unsigned long flags;
0162     void __iomem *mdrefr = pxa_smemc_get_mdrefr();
0163
0164     local_irq_save(flags);
0165
0166     /* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
0167      * we need to preset the smaller DRI before the change.  If we're
0168      * speeding up we need to set the larger DRI value after the change.
0169      */
0170     preset_mdrefr = postset_mdrefr = readl(mdrefr);
0171     if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(freq->membus_khz)) {
0172         preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
0173         preset_mdrefr |= mdrefr_dri(freq->membus_khz);
0174     }
0175     postset_mdrefr =
0176         (postset_mdrefr & ~MDREFR_DRI_MASK) |
0177         mdrefr_dri(freq->membus_khz);
0178
0179     /* If we're dividing the memory clock by two for the SDRAM clock, this
0180      * must be set prior to the change.  Clearing the divide must be done
0181      * after the change.
0182      */
0183     if (freq->div2) {
0184         preset_mdrefr  |= MDREFR_DB2_MASK;
0185         postset_mdrefr |= MDREFR_DB2_MASK;
0186     } else {
0187         postset_mdrefr &= ~MDREFR_DB2_MASK;
0188     }
0189
0190     /* Set new the CCCR and prepare CLKCFG */
0191     writel(freq->cccr, cccr);
0192
0193     asm volatile(
0194     "   ldr r4, [%1]\n"
0195     "   b   2f\n"
0196     "   .align  5\n"
0197     "1: str %3, [%1]        /* preset the MDREFR */\n"
0198     "   mcr p14, 0, %2, c6, c0, 0   /* set CLKCFG[FCS] */\n"
0199     "   str %4, [%1]        /* postset the MDREFR */\n"
0200     "   b   3f\n"
0201     "2: b   1b\n"
0202     "3: nop\n"
0203          : "=&r" (unused)
0204          : "r" (mdrefr), "r" (clkcfg), "r" (preset_mdrefr),
0205            "r" (postset_mdrefr)
0206          : "r4", "r5");
0207
0208     local_irq_restore(flags);
0209 }
0210
0211 int pxa2xx_determine_rate(struct clk_rate_request *req,
0212               struct pxa2xx_freq *freqs, int nb_freqs)
0213 {
0214     int i, closest_below = -1, closest_above = -1;
0215     unsigned long rate;
0216
0217     for (i = 0; i < nb_freqs; i++) {
0218         rate = freqs[i].cpll;
0219         if (rate == req->rate)
0220             break;
0221         if (rate < req->min_rate)
0222             continue;
0223         if (rate > req->max_rate)
0224             continue;
0225         if (rate <= req->rate)
0226             closest_below = i;
0227         if ((rate >= req->rate) && (closest_above == -1))
0228             closest_above = i;
0229     }
0230
0231     req->best_parent_hw = NULL;
0232
0233     if (i < nb_freqs) {
0234         rate = req->rate;
0235     } else if (closest_below >= 0) {
0236         rate = freqs[closest_below].cpll;
0237     } else if (closest_above >= 0) {
0238         rate = freqs[closest_above].cpll;
0239     } else {
0240         pr_debug("%s(rate=%lu) no match\n", __func__, req->rate);
0241         return -EINVAL;
0242     }
0243
0244     pr_debug("%s(rate=%lu) rate=%lu\n", __func__, req->rate, rate);
0245     req->rate = rate;
0246
0247     return 0;
0248 }