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0008 #include <linux/clk-provider.h>
0009 #include <linux/init.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/of.h>
0013
0014 #include <dt-bindings/clock/pistachio-clk.h>
0015
0016 #include "clk.h"
0017
0018 static struct pistachio_gate pistachio_gates[] __initdata = {
0019 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
0020 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
0021 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
0022 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
0023 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
0024 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
0025 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
0026 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
0027 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
0028 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
0029 GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
0030 GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
0031 GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
0032 GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
0033 GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
0034 GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
0035 GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
0036 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
0037 GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
0038 GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
0039 GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
0040 GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
0041 GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
0042 0x104, 22),
0043 GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
0044 GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
0045 GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
0046 GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
0047 GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
0048 GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
0049 };
0050
0051 static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
0052 FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
0053 FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
0054 };
0055
0056 static struct pistachio_div pistachio_divs[] __initdata = {
0057 DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",
0058 0x204, 2),
0059 DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
0060 DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",
0061 0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),
0062 DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",
0063 0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),
0064 DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",
0065 0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),
0066 DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",
0067 0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),
0068 DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
0069 DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
0070 DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
0071 DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
0072 DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
0073 DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
0074 DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
0075 0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),
0076 DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
0077 CLK_DIVIDER_ROUND_CLOSEST),
0078 DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",
0079 0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),
0080 DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
0081 CLK_DIVIDER_ROUND_CLOSEST),
0082 DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
0083 DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",
0084 0x248, 3),
0085 DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),
0086 DIV(CLK_SPI1_INTERNAL_DIV, "spi1_internal_div", "sys_pll_mux",
0087 0x250, 3),
0088 DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),
0089 DIV(CLK_EVENT_TIMER_INTERNAL_DIV, "event_timer_internal_div",
0090 "event_timer_mux", 0x258, 3),
0091 DIV(CLK_EVENT_TIMER_DIV, "event_timer_div", "event_timer_internal_div",
0092 0x25c, 12),
0093 DIV(CLK_AUX_ADC_INTERNAL_DIV, "aux_adc_internal_div",
0094 "aux_adc_internal", 0x260, 3),
0095 DIV(CLK_AUX_ADC_DIV, "aux_adc_div", "aux_adc_internal_div", 0x264, 10),
0096 DIV(CLK_SD_HOST_DIV, "sd_host_div", "sd_host_mux", 0x268, 6),
0097 DIV(CLK_BT_DIV, "bt_div", "bt_pll_mux", 0x26c, 6),
0098 DIV(CLK_BT_DIV4_DIV, "bt_div4_div", "bt_pll_mux", 0x270, 6),
0099 DIV(CLK_BT_DIV8_DIV, "bt_div8_div", "bt_pll_mux", 0x274, 6),
0100 DIV(CLK_BT_1MHZ_INTERNAL_DIV, "bt_1mhz_internal_div", "bt_pll_mux",
0101 0x278, 3),
0102 DIV(CLK_BT_1MHZ_DIV, "bt_1mhz_div", "bt_1mhz_internal_div", 0x27c, 10),
0103 };
0104
0105 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
0106 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
0107 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
0108 PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
0109 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
0110 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
0111 PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
0112 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
0113 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
0114 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
0115 PNAME(mux_wifi_div4_rpu_l) = { "wifi_pll_gate", "wifi_div4_mux",
0116 "rpu_l_pll_mux" };
0117 PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
0118 PNAME(mux_sys_enet) = { "sys_internal_div", "enet_in" };
0119 PNAME(mux_audio_sys) = { "audio_pll_mux", "sys_internal_div" };
0120 PNAME(mux_sys_bt) = { "sys_internal_div", "bt_pll_mux" };
0121 PNAME(mux_xtal_bt) = { "xtal", "bt_pll" };
0122
0123 static struct pistachio_mux pistachio_muxes[] __initdata = {
0124 MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
0125 0x200, 0),
0126 MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
0127 MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
0128 MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
0129 MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
0130 MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
0131 MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
0132 MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
0133 MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
0134 MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
0135 MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11),
0136 MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),
0137 MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),
0138 MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15),
0139 MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),
0140 MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
0141 };
0142
0143 static struct pistachio_pll pistachio_plls[] __initdata = {
0144 PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),
0145 PLL_FIXED(CLK_AUDIO_PLL, "audio_pll", "audio_refclk_mux",
0146 PLL_GF40LP_FRAC, 0xc),
0147 PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),
0148 PLL_FIXED(CLK_RPU_L_PLL, "rpu_l_pll", "xtal", PLL_GF40LP_LAINT, 0x2c),
0149 PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),
0150 PLL_FIXED(CLK_WIFI_PLL, "wifi_pll", "xtal", PLL_GF40LP_FRAC, 0x4c),
0151 PLL_FIXED(CLK_BT_PLL, "bt_pll", "xtal", PLL_GF40LP_LAINT, 0x60),
0152 };
0153
0154 PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux",
0155 "rpu_l_pll_mux", "sys_pll_mux",
0156 "wifi_pll_mux", "bt_pll_mux" };
0157 static const u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
0158
0159 static unsigned int pistachio_critical_clks_core[] __initdata = {
0160 CLK_MIPS
0161 };
0162
0163 static unsigned int pistachio_critical_clks_sys[] __initdata = {
0164 PERIPH_CLK_SYS,
0165 PERIPH_CLK_SYS_BUS,
0166 PERIPH_CLK_DDR,
0167 PERIPH_CLK_ROM,
0168 };
0169
0170 static void __init pistachio_clk_init(struct device_node *np)
0171 {
0172 struct pistachio_clk_provider *p;
0173 struct clk *debug_clk;
0174
0175 p = pistachio_clk_alloc_provider(np, CLK_NR_CLKS);
0176 if (!p)
0177 return;
0178
0179 pistachio_clk_register_pll(p, pistachio_plls,
0180 ARRAY_SIZE(pistachio_plls));
0181 pistachio_clk_register_mux(p, pistachio_muxes,
0182 ARRAY_SIZE(pistachio_muxes));
0183 pistachio_clk_register_div(p, pistachio_divs,
0184 ARRAY_SIZE(pistachio_divs));
0185 pistachio_clk_register_fixed_factor(p, pistachio_ffs,
0186 ARRAY_SIZE(pistachio_ffs));
0187 pistachio_clk_register_gate(p, pistachio_gates,
0188 ARRAY_SIZE(pistachio_gates));
0189
0190 debug_clk = clk_register_mux_table(NULL, "debug_mux", mux_debug,
0191 ARRAY_SIZE(mux_debug),
0192 CLK_SET_RATE_NO_REPARENT,
0193 p->base + 0x200, 18, 0x1f, 0,
0194 mux_debug_idx, NULL);
0195 p->clk_data.clks[CLK_DEBUG_MUX] = debug_clk;
0196
0197 pistachio_clk_register_provider(p);
0198
0199 pistachio_clk_force_enable(p, pistachio_critical_clks_core,
0200 ARRAY_SIZE(pistachio_critical_clks_core));
0201 }
0202 CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);
0203
0204 static struct pistachio_gate pistachio_periph_gates[] __initdata = {
0205 GATE(PERIPH_CLK_SYS, "sys", "periph_sys", 0x100, 0),
0206 GATE(PERIPH_CLK_SYS_BUS, "bus_sys", "periph_sys", 0x100, 1),
0207 GATE(PERIPH_CLK_DDR, "ddr", "periph_sys", 0x100, 2),
0208 GATE(PERIPH_CLK_ROM, "rom", "rom_div", 0x100, 3),
0209 GATE(PERIPH_CLK_COUNTER_FAST, "counter_fast", "counter_fast_div",
0210 0x100, 4),
0211 GATE(PERIPH_CLK_COUNTER_SLOW, "counter_slow", "counter_slow_div",
0212 0x100, 5),
0213 GATE(PERIPH_CLK_IR, "ir", "ir_div", 0x100, 6),
0214 GATE(PERIPH_CLK_WD, "wd", "wd_div", 0x100, 7),
0215 GATE(PERIPH_CLK_PDM, "pdm", "pdm_div", 0x100, 8),
0216 GATE(PERIPH_CLK_PWM, "pwm", "pwm_div", 0x100, 9),
0217 GATE(PERIPH_CLK_I2C0, "i2c0", "i2c0_div", 0x100, 10),
0218 GATE(PERIPH_CLK_I2C1, "i2c1", "i2c1_div", 0x100, 11),
0219 GATE(PERIPH_CLK_I2C2, "i2c2", "i2c2_div", 0x100, 12),
0220 GATE(PERIPH_CLK_I2C3, "i2c3", "i2c3_div", 0x100, 13),
0221 };
0222
0223 static struct pistachio_div pistachio_periph_divs[] __initdata = {
0224 DIV(PERIPH_CLK_ROM_DIV, "rom_div", "periph_sys", 0x10c, 7),
0225 DIV(PERIPH_CLK_COUNTER_FAST_DIV, "counter_fast_div", "periph_sys",
0226 0x110, 7),
0227 DIV(PERIPH_CLK_COUNTER_SLOW_PRE_DIV, "counter_slow_pre_div",
0228 "periph_sys", 0x114, 7),
0229 DIV(PERIPH_CLK_COUNTER_SLOW_DIV, "counter_slow_div",
0230 "counter_slow_pre_div", 0x118, 7),
0231 DIV_F(PERIPH_CLK_IR_PRE_DIV, "ir_pre_div", "periph_sys", 0x11c, 7,
0232 CLK_DIVIDER_ROUND_CLOSEST),
0233 DIV_F(PERIPH_CLK_IR_DIV, "ir_div", "ir_pre_div", 0x120, 7,
0234 CLK_DIVIDER_ROUND_CLOSEST),
0235 DIV_F(PERIPH_CLK_WD_PRE_DIV, "wd_pre_div", "periph_sys", 0x124, 7,
0236 CLK_DIVIDER_ROUND_CLOSEST),
0237 DIV_F(PERIPH_CLK_WD_DIV, "wd_div", "wd_pre_div", 0x128, 7,
0238 CLK_DIVIDER_ROUND_CLOSEST),
0239 DIV(PERIPH_CLK_PDM_PRE_DIV, "pdm_pre_div", "periph_sys", 0x12c, 7),
0240 DIV(PERIPH_CLK_PDM_DIV, "pdm_div", "pdm_pre_div", 0x130, 7),
0241 DIV(PERIPH_CLK_PWM_PRE_DIV, "pwm_pre_div", "periph_sys", 0x134, 7),
0242 DIV(PERIPH_CLK_PWM_DIV, "pwm_div", "pwm_pre_div", 0x138, 7),
0243 DIV(PERIPH_CLK_I2C0_PRE_DIV, "i2c0_pre_div", "periph_sys", 0x13c, 7),
0244 DIV(PERIPH_CLK_I2C0_DIV, "i2c0_div", "i2c0_pre_div", 0x140, 7),
0245 DIV(PERIPH_CLK_I2C1_PRE_DIV, "i2c1_pre_div", "periph_sys", 0x144, 7),
0246 DIV(PERIPH_CLK_I2C1_DIV, "i2c1_div", "i2c1_pre_div", 0x148, 7),
0247 DIV(PERIPH_CLK_I2C2_PRE_DIV, "i2c2_pre_div", "periph_sys", 0x14c, 7),
0248 DIV(PERIPH_CLK_I2C2_DIV, "i2c2_div", "i2c2_pre_div", 0x150, 7),
0249 DIV(PERIPH_CLK_I2C3_PRE_DIV, "i2c3_pre_div", "periph_sys", 0x154, 7),
0250 DIV(PERIPH_CLK_I2C3_DIV, "i2c3_div", "i2c3_pre_div", 0x158, 7),
0251 };
0252
0253 static void __init pistachio_clk_periph_init(struct device_node *np)
0254 {
0255 struct pistachio_clk_provider *p;
0256
0257 p = pistachio_clk_alloc_provider(np, PERIPH_CLK_NR_CLKS);
0258 if (!p)
0259 return;
0260
0261 pistachio_clk_register_div(p, pistachio_periph_divs,
0262 ARRAY_SIZE(pistachio_periph_divs));
0263 pistachio_clk_register_gate(p, pistachio_periph_gates,
0264 ARRAY_SIZE(pistachio_periph_gates));
0265
0266 pistachio_clk_register_provider(p);
0267
0268 pistachio_clk_force_enable(p, pistachio_critical_clks_sys,
0269 ARRAY_SIZE(pistachio_critical_clks_sys));
0270 }
0271 CLK_OF_DECLARE(pistachio_clk_periph, "img,pistachio-clk-periph",
0272 pistachio_clk_periph_init);
0273
0274 static struct pistachio_gate pistachio_sys_gates[] __initdata = {
0275 GATE(SYS_CLK_I2C0, "i2c0_sys", "sys", 0x8, 0),
0276 GATE(SYS_CLK_I2C1, "i2c1_sys", "sys", 0x8, 1),
0277 GATE(SYS_CLK_I2C2, "i2c2_sys", "sys", 0x8, 2),
0278 GATE(SYS_CLK_I2C3, "i2c3_sys", "sys", 0x8, 3),
0279 GATE(SYS_CLK_I2S_IN, "i2s_in_sys", "sys", 0x8, 4),
0280 GATE(SYS_CLK_PAUD_OUT, "paud_out_sys", "sys", 0x8, 5),
0281 GATE(SYS_CLK_SPDIF_OUT, "spdif_out_sys", "sys", 0x8, 6),
0282 GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),
0283 GATE(SYS_CLK_SPI0_SLAVE, "spi0_slave_sys", "sys", 0x8, 8),
0284 GATE(SYS_CLK_PWM, "pwm_sys", "sys", 0x8, 9),
0285 GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),
0286 GATE(SYS_CLK_UART1, "uart1_sys", "sys", 0x8, 11),
0287 GATE(SYS_CLK_SPI1, "spi1_sys", "sys", 0x8, 12),
0288 GATE(SYS_CLK_MDC, "mdc_sys", "sys", 0x8, 13),
0289 GATE(SYS_CLK_SD_HOST, "sd_host_sys", "sys", 0x8, 14),
0290 GATE(SYS_CLK_ENET, "enet_sys", "sys", 0x8, 15),
0291 GATE(SYS_CLK_IR, "ir_sys", "sys", 0x8, 16),
0292 GATE(SYS_CLK_WD, "wd_sys", "sys", 0x8, 17),
0293 GATE(SYS_CLK_TIMER, "timer_sys", "sys", 0x8, 18),
0294 GATE(SYS_CLK_I2S_OUT, "i2s_out_sys", "sys", 0x8, 24),
0295 GATE(SYS_CLK_SPDIF_IN, "spdif_in_sys", "sys", 0x8, 25),
0296 GATE(SYS_CLK_EVENT_TIMER, "event_timer_sys", "sys", 0x8, 26),
0297 GATE(SYS_CLK_HASH, "hash_sys", "sys", 0x8, 27),
0298 };
0299
0300 static void __init pistachio_cr_periph_init(struct device_node *np)
0301 {
0302 struct pistachio_clk_provider *p;
0303
0304 p = pistachio_clk_alloc_provider(np, SYS_CLK_NR_CLKS);
0305 if (!p)
0306 return;
0307
0308 pistachio_clk_register_gate(p, pistachio_sys_gates,
0309 ARRAY_SIZE(pistachio_sys_gates));
0310
0311 pistachio_clk_register_provider(p);
0312 }
0313 CLK_OF_DECLARE(pistachio_cr_periph, "img,pistachio-cr-periph",
0314 pistachio_cr_periph_init);
0315
0316 static struct pistachio_gate pistachio_ext_gates[] __initdata = {
0317 GATE(EXT_CLK_ENET_IN, "enet_clk_in_gate", "enet_clk_in", 0x58, 5),
0318 GATE(EXT_CLK_AUDIO_IN, "audio_clk_in_gate", "audio_clk_in", 0x58, 8)
0319 };
0320
0321 static void __init pistachio_cr_top_init(struct device_node *np)
0322 {
0323 struct pistachio_clk_provider *p;
0324
0325 p = pistachio_clk_alloc_provider(np, EXT_CLK_NR_CLKS);
0326 if (!p)
0327 return;
0328
0329 pistachio_clk_register_gate(p, pistachio_ext_gates,
0330 ARRAY_SIZE(pistachio_ext_gates));
0331
0332 pistachio_clk_register_provider(p);
0333 }
0334 CLK_OF_DECLARE(pistachio_cr_top, "img,pistachio-cr-top",
0335 pistachio_cr_top_init);
