clk/nxp/clk-lpc18xx-creg.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Clk driver for NXP LPC18xx/43xx Configuration Registers (CREG)
0004  *
0005  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/delay.h>
0010 #include <linux/kernel.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/of.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015
0016 #define LPC18XX_CREG_CREG0          0x004
0017 #define  LPC18XX_CREG_CREG0_EN1KHZ      BIT(0)
0018 #define  LPC18XX_CREG_CREG0_EN32KHZ     BIT(1)
0019 #define  LPC18XX_CREG_CREG0_RESET32KHZ      BIT(2)
0020 #define  LPC18XX_CREG_CREG0_PD32KHZ     BIT(3)
0021
0022 #define to_clk_creg(_hw) container_of(_hw, struct clk_creg_data, hw)
0023
0024 enum {
0025     CREG_CLK_1KHZ,
0026     CREG_CLK_32KHZ,
0027     CREG_CLK_MAX,
0028 };
0029
0030 struct clk_creg_data {
0031     struct clk_hw hw;
0032     const char *name;
0033     struct regmap *reg;
0034     unsigned int en_mask;
0035     const struct clk_ops *ops;
0036 };
0037
0038 #define CREG_CLK(_name, _emask, _ops)       \
0039 {                       \
0040     .name = _name,              \
0041     .en_mask = LPC18XX_CREG_CREG0_##_emask, \
0042     .ops = &_ops,               \
0043 }
0044
0045 static int clk_creg_32k_prepare(struct clk_hw *hw)
0046 {
0047     struct clk_creg_data *creg = to_clk_creg(hw);
0048     int ret;
0049
0050     ret = regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
0051                  LPC18XX_CREG_CREG0_PD32KHZ |
0052                  LPC18XX_CREG_CREG0_RESET32KHZ, 0);
0053
0054     /*
0055      * Powering up the 32k oscillator takes a long while
0056      * and sadly there aren't any status bit to poll.
0057      */
0058     msleep(2500);
0059
0060     return ret;
0061 }
0062
0063 static void clk_creg_32k_unprepare(struct clk_hw *hw)
0064 {
0065     struct clk_creg_data *creg = to_clk_creg(hw);
0066
0067     regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
0068                LPC18XX_CREG_CREG0_PD32KHZ,
0069                LPC18XX_CREG_CREG0_PD32KHZ);
0070 }
0071
0072 static int clk_creg_32k_is_prepared(struct clk_hw *hw)
0073 {
0074     struct clk_creg_data *creg = to_clk_creg(hw);
0075     u32 reg;
0076
0077     regmap_read(creg->reg, LPC18XX_CREG_CREG0, &reg);
0078
0079     return !(reg & LPC18XX_CREG_CREG0_PD32KHZ) &&
0080            !(reg & LPC18XX_CREG_CREG0_RESET32KHZ);
0081 }
0082
0083 static unsigned long clk_creg_1k_recalc_rate(struct clk_hw *hw,
0084                          unsigned long parent_rate)
0085 {
0086     return parent_rate / 32;
0087 }
0088
0089 static int clk_creg_enable(struct clk_hw *hw)
0090 {
0091     struct clk_creg_data *creg = to_clk_creg(hw);
0092
0093     return regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
0094                   creg->en_mask, creg->en_mask);
0095 }
0096
0097 static void clk_creg_disable(struct clk_hw *hw)
0098 {
0099     struct clk_creg_data *creg = to_clk_creg(hw);
0100
0101     regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
0102                creg->en_mask, 0);
0103 }
0104
0105 static int clk_creg_is_enabled(struct clk_hw *hw)
0106 {
0107     struct clk_creg_data *creg = to_clk_creg(hw);
0108     u32 reg;
0109
0110     regmap_read(creg->reg, LPC18XX_CREG_CREG0, &reg);
0111
0112     return !!(reg & creg->en_mask);
0113 }
0114
0115 static const struct clk_ops clk_creg_32k = {
0116     .enable     = clk_creg_enable,
0117     .disable    = clk_creg_disable,
0118     .is_enabled = clk_creg_is_enabled,
0119     .prepare    = clk_creg_32k_prepare,
0120     .unprepare  = clk_creg_32k_unprepare,
0121     .is_prepared    = clk_creg_32k_is_prepared,
0122 };
0123
0124 static const struct clk_ops clk_creg_1k = {
0125     .enable     = clk_creg_enable,
0126     .disable    = clk_creg_disable,
0127     .is_enabled = clk_creg_is_enabled,
0128     .recalc_rate    = clk_creg_1k_recalc_rate,
0129 };
0130
0131 static struct clk_creg_data clk_creg_clocks[] = {
0132     [CREG_CLK_1KHZ]  = CREG_CLK("1khz_clk",  EN1KHZ,  clk_creg_1k),
0133     [CREG_CLK_32KHZ] = CREG_CLK("32khz_clk", EN32KHZ, clk_creg_32k),
0134 };
0135
0136 static struct clk *clk_register_creg_clk(struct device *dev,
0137                      struct clk_creg_data *creg_clk,
0138                      const char **parent_name,
0139                      struct regmap *syscon)
0140 {
0141     struct clk_init_data init;
0142
0143     init.ops = creg_clk->ops;
0144     init.name = creg_clk->name;
0145     init.parent_names = parent_name;
0146     init.num_parents = 1;
0147     init.flags = 0;
0148
0149     creg_clk->reg = syscon;
0150     creg_clk->hw.init = &init;
0151
0152     if (dev)
0153         return devm_clk_register(dev, &creg_clk->hw);
0154
0155     return clk_register(NULL, &creg_clk->hw);
0156 }
0157
0158 static struct clk *clk_creg_early[CREG_CLK_MAX];
0159 static struct clk_onecell_data clk_creg_early_data = {
0160     .clks = clk_creg_early,
0161     .clk_num = CREG_CLK_MAX,
0162 };
0163
0164 static void __init lpc18xx_creg_clk_init(struct device_node *np)
0165 {
0166     const char *clk_32khz_parent;
0167     struct regmap *syscon;
0168
0169     syscon = syscon_node_to_regmap(np->parent);
0170     if (IS_ERR(syscon)) {
0171         pr_err("%s: syscon lookup failed\n", __func__);
0172         return;
0173     }
0174
0175     clk_32khz_parent = of_clk_get_parent_name(np, 0);
0176
0177     clk_creg_early[CREG_CLK_32KHZ] =
0178         clk_register_creg_clk(NULL, &clk_creg_clocks[CREG_CLK_32KHZ],
0179                       &clk_32khz_parent, syscon);
0180     clk_creg_early[CREG_CLK_1KHZ] = ERR_PTR(-EPROBE_DEFER);
0181
0182     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_creg_early_data);
0183 }
0184 CLK_OF_DECLARE_DRIVER(lpc18xx_creg_clk, "nxp,lpc1850-creg-clk",
0185               lpc18xx_creg_clk_init);
0186
0187 static struct clk *clk_creg[CREG_CLK_MAX];
0188 static struct clk_onecell_data clk_creg_data = {
0189     .clks = clk_creg,
0190     .clk_num = CREG_CLK_MAX,
0191 };
0192
0193 static int lpc18xx_creg_clk_probe(struct platform_device *pdev)
0194 {
0195     struct device_node *np = pdev->dev.of_node;
0196     struct regmap *syscon;
0197
0198     syscon = syscon_node_to_regmap(np->parent);
0199     if (IS_ERR(syscon)) {
0200         dev_err(&pdev->dev, "syscon lookup failed\n");
0201         return PTR_ERR(syscon);
0202     }
0203
0204     clk_creg[CREG_CLK_32KHZ] = clk_creg_early[CREG_CLK_32KHZ];
0205     clk_creg[CREG_CLK_1KHZ] =
0206         clk_register_creg_clk(NULL, &clk_creg_clocks[CREG_CLK_1KHZ],
0207                       &clk_creg_clocks[CREG_CLK_32KHZ].name,
0208                       syscon);
0209
0210     return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_creg_data);
0211 }
0212
0213 static const struct of_device_id lpc18xx_creg_clk_of_match[] = {
0214     { .compatible = "nxp,lpc1850-creg-clk" },
0215     {},
0216 };
0217
0218 static struct platform_driver lpc18xx_creg_clk_driver = {
0219     .probe = lpc18xx_creg_clk_probe,
0220     .driver = {
0221         .name = "lpc18xx-creg-clk",
0222         .of_match_table = lpc18xx_creg_clk_of_match,
0223     },
0224 };
0225 builtin_platform_driver(lpc18xx_creg_clk_driver);