clk/mxs/clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2012 Freescale Semiconductor, Inc.
0004  */
0005
0006 #ifndef __MXS_CLK_H
0007 #define __MXS_CLK_H
0008
0009 struct clk;
0010
0011 #include <linux/clk-provider.h>
0012 #include <linux/spinlock.h>
0013
0014 #define SET 0x4
0015 #define CLR 0x8
0016
0017 extern spinlock_t mxs_lock;
0018
0019 int mxs_clk_wait(void __iomem *reg, u8 shift);
0020
0021 struct clk *mxs_clk_pll(const char *name, const char *parent_name,
0022             void __iomem *base, u8 power, unsigned long rate);
0023
0024 struct clk *mxs_clk_ref(const char *name, const char *parent_name,
0025             void __iomem *reg, u8 idx);
0026
0027 struct clk *mxs_clk_div(const char *name, const char *parent_name,
0028             void __iomem *reg, u8 shift, u8 width, u8 busy);
0029
0030 struct clk *mxs_clk_frac(const char *name, const char *parent_name,
0031              void __iomem *reg, u8 shift, u8 width, u8 busy);
0032
0033 static inline struct clk *mxs_clk_fixed(const char *name, int rate)
0034 {
0035     return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
0036 }
0037
0038 static inline struct clk *mxs_clk_gate(const char *name,
0039             const char *parent_name, void __iomem *reg, u8 shift)
0040 {
0041     return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT,
0042                  reg, shift, CLK_GATE_SET_TO_DISABLE,
0043                  &mxs_lock);
0044 }
0045
0046 static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
0047         u8 shift, u8 width, const char *const *parent_names, int num_parents)
0048 {
0049     return clk_register_mux(NULL, name, parent_names, num_parents,
0050                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0051                 reg, shift, width, 0, &mxs_lock);
0052 }
0053
0054 static inline struct clk *mxs_clk_fixed_factor(const char *name,
0055         const char *parent_name, unsigned int mult, unsigned int div)
0056 {
0057     return clk_register_fixed_factor(NULL, name, parent_name,
0058                      CLK_SET_RATE_PARENT, mult, div);
0059 }
0060
0061 #endif /* __MXS_CLK_H */