clk/mxs/clk-ssp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2012 DENX Software Engineering, GmbH
0004  *
0005  * Pulled from code:
0006  * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
0007  * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
0008  *
0009  * Copyright 2008 Embedded Alley Solutions, Inc.
0010  * Copyright 2009-2011 Freescale Semiconductor, Inc.
0011  */
0012
0013 #include <linux/kernel.h>
0014 #include <linux/init.h>
0015 #include <linux/clk.h>
0016 #include <linux/module.h>
0017 #include <linux/device.h>
0018 #include <linux/io.h>
0019 #include <linux/spi/mxs-spi.h>
0020
0021 void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate)
0022 {
0023     unsigned int ssp_clk, ssp_sck;
0024     u32 clock_divide, clock_rate;
0025     u32 val;
0026
0027     ssp_clk = clk_get_rate(ssp->clk);
0028
0029     for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
0030         clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
0031         clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
0032         if (clock_rate <= 255)
0033             break;
0034     }
0035
0036     if (clock_divide > 254) {
0037         dev_err(ssp->dev,
0038             "%s: cannot set clock to %d\n", __func__, rate);
0039         return;
0040     }
0041
0042     ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
0043
0044     val = readl(ssp->base + HW_SSP_TIMING(ssp));
0045     val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
0046     val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
0047     val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
0048     writel(val, ssp->base + HW_SSP_TIMING(ssp));
0049
0050     ssp->clk_rate = ssp_sck;
0051
0052     dev_dbg(ssp->dev,
0053         "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
0054         __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
0055 }
0056 EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);