clk/mxs/clk-imx28.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2012 Freescale Semiconductor, Inc.
0004  */
0005
0006 #include <linux/clk/mxs.h>
0007 #include <linux/clkdev.h>
0008 #include <linux/clk.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/err.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include "clk.h"
0016
0017 static void __iomem *clkctrl;
0018 #define CLKCTRL clkctrl
0019
0020 #define PLL0CTRL0       (CLKCTRL + 0x0000)
0021 #define PLL1CTRL0       (CLKCTRL + 0x0020)
0022 #define PLL2CTRL0       (CLKCTRL + 0x0040)
0023 #define CPU         (CLKCTRL + 0x0050)
0024 #define HBUS            (CLKCTRL + 0x0060)
0025 #define XBUS            (CLKCTRL + 0x0070)
0026 #define XTAL            (CLKCTRL + 0x0080)
0027 #define SSP0            (CLKCTRL + 0x0090)
0028 #define SSP1            (CLKCTRL + 0x00a0)
0029 #define SSP2            (CLKCTRL + 0x00b0)
0030 #define SSP3            (CLKCTRL + 0x00c0)
0031 #define GPMI            (CLKCTRL + 0x00d0)
0032 #define SPDIF           (CLKCTRL + 0x00e0)
0033 #define EMI         (CLKCTRL + 0x00f0)
0034 #define SAIF0           (CLKCTRL + 0x0100)
0035 #define SAIF1           (CLKCTRL + 0x0110)
0036 #define LCDIF           (CLKCTRL + 0x0120)
0037 #define ETM         (CLKCTRL + 0x0130)
0038 #define ENET            (CLKCTRL + 0x0140)
0039 #define FLEXCAN         (CLKCTRL + 0x0160)
0040 #define FRAC0           (CLKCTRL + 0x01b0)
0041 #define FRAC1           (CLKCTRL + 0x01c0)
0042 #define CLKSEQ          (CLKCTRL + 0x01d0)
0043
0044 #define BP_CPU_INTERRUPT_WAIT   12
0045 #define BP_SAIF_DIV_FRAC_EN 16
0046 #define BP_ENET_DIV_TIME    21
0047 #define BP_ENET_SLEEP       31
0048 #define BP_CLKSEQ_BYPASS_SAIF0  0
0049 #define BP_CLKSEQ_BYPASS_SSP0   3
0050 #define BP_FRAC0_IO1FRAC    16
0051 #define BP_FRAC0_IO0FRAC    24
0052
0053 static void __iomem *digctrl;
0054 #define DIGCTRL digctrl
0055 #define BP_SAIF_CLKMUX      10
0056
0057 /*
0058  * HW_SAIF_CLKMUX_SEL:
0059  *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
0060  *      clock pins selected for SAIF1 input clocks.
0061  *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
0062  *      SAIF0 clock inputs selected for SAIF1 input clocks.
0063  *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
0064  *      clocks.
0065  *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
0066  *      clocks.
0067  */
0068 int mxs_saif_clkmux_select(unsigned int clkmux)
0069 {
0070     if (clkmux > 0x3)
0071         return -EINVAL;
0072
0073     writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
0074     writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
0075
0076     return 0;
0077 }
0078
0079 static void __init clk_misc_init(void)
0080 {
0081     u32 val;
0082
0083     /* Gate off cpu clock in WFI for power saving */
0084     writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
0085
0086     /* 0 is a bad default value for a divider */
0087     writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
0088
0089     /* Clear BYPASS for SAIF */
0090     writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
0091
0092     /* SAIF has to use frac div for functional operation */
0093     val = readl_relaxed(SAIF0);
0094     val |= 1 << BP_SAIF_DIV_FRAC_EN;
0095     writel_relaxed(val, SAIF0);
0096
0097     val = readl_relaxed(SAIF1);
0098     val |= 1 << BP_SAIF_DIV_FRAC_EN;
0099     writel_relaxed(val, SAIF1);
0100
0101     /* Extra fec clock setting */
0102     val = readl_relaxed(ENET);
0103     val &= ~(1 << BP_ENET_SLEEP);
0104     writel_relaxed(val, ENET);
0105
0106     /*
0107      * Source ssp clock from ref_io than ref_xtal,
0108      * as ref_xtal only provides 24 MHz as maximum.
0109      */
0110     writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
0111
0112     /*
0113      * 480 MHz seems too high to be ssp clock source directly,
0114      * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
0115      */
0116     val = readl_relaxed(FRAC0);
0117     val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
0118     val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
0119     writel_relaxed(val, FRAC0);
0120 }
0121
0122 static const char *const sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
0123 static const char *const sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
0124 static const char *const sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
0125 static const char *const sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
0126 static const char *const sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
0127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
0128 static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
0129 static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
0130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
0131
0132 enum imx28_clk {
0133     ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
0134     ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
0135     ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
0136     lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
0137     ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
0138     emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
0139     clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
0140     ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
0141     fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
0142     clk_max
0143 };
0144
0145 static struct clk *clks[clk_max];
0146 static struct clk_onecell_data clk_data;
0147
0148 static enum imx28_clk clks_init_on[] __initdata = {
0149     cpu, hbus, xbus, emi, uart,
0150 };
0151
0152 static void __init mx28_clocks_init(struct device_node *np)
0153 {
0154     struct device_node *dcnp;
0155     u32 i;
0156
0157     dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
0158     digctrl = of_iomap(dcnp, 0);
0159     WARN_ON(!digctrl);
0160     of_node_put(dcnp);
0161
0162     clkctrl = of_iomap(np, 0);
0163     WARN_ON(!clkctrl);
0164
0165     clk_misc_init();
0166
0167     clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
0168     clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
0169     clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
0170     clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
0171     clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
0172     clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
0173     clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
0174     clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
0175     clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
0176     clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
0177     clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
0178     clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
0179     clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
0180     clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
0181     clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
0182     clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
0183     clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
0184     clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
0185     clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
0186     clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
0187     clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
0188     clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
0189     clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
0190     clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
0191     clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
0192     clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
0193     clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
0194     clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
0195     clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
0196     clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
0197     clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
0198     clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
0199     clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
0200     clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
0201     clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
0202     clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
0203     clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27);
0204     clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
0205     clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);
0206     clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
0207     clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
0208     clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
0209     clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4);
0210     clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
0211     clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
0212     clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
0213     clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
0214     clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
0215     clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
0216     clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
0217     clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
0218     clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
0219     clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
0220     clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);
0221     clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);
0222     clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
0223     clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
0224     clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
0225     clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
0226     clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
0227     clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
0228     clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
0229     clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
0230     clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
0231     clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
0232
0233     for (i = 0; i < ARRAY_SIZE(clks); i++)
0234         if (IS_ERR(clks[i])) {
0235             pr_err("i.MX28 clk %d: register failed with %ld\n",
0236                 i, PTR_ERR(clks[i]));
0237             return;
0238         }
0239
0240     clk_data.clks = clks;
0241     clk_data.clk_num = ARRAY_SIZE(clks);
0242     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
0243
0244     clk_register_clkdev(clks[enet_out], NULL, "enet_out");
0245
0246     for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
0247         clk_prepare_enable(clks[clks_init_on[i]]);
0248 }
0249 CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init);