clk/mxs/clk-frac.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2012 Freescale Semiconductor, Inc.
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/err.h>
0008 #include <linux/io.h>
0009 #include <linux/slab.h>
0010 #include "clk.h"
0011
0012 /**
0013  * struct clk_frac - mxs fractional divider clock
0014  * @hw: clk_hw for the fractional divider clock
0015  * @reg: register address
0016  * @shift: the divider bit shift
0017  * @width: the divider bit width
0018  * @busy: busy bit shift
0019  *
0020  * The clock is an adjustable fractional divider with a busy bit to wait
0021  * when the divider is adjusted.
0022  */
0023 struct clk_frac {
0024     struct clk_hw hw;
0025     void __iomem *reg;
0026     u8 shift;
0027     u8 width;
0028     u8 busy;
0029 };
0030
0031 #define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
0032
0033 static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
0034                       unsigned long parent_rate)
0035 {
0036     struct clk_frac *frac = to_clk_frac(hw);
0037     u32 div;
0038     u64 tmp_rate;
0039
0040     div = readl_relaxed(frac->reg) >> frac->shift;
0041     div &= (1 << frac->width) - 1;
0042
0043     tmp_rate = (u64)parent_rate * div;
0044     return tmp_rate >> frac->width;
0045 }
0046
0047 static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
0048                 unsigned long *prate)
0049 {
0050     struct clk_frac *frac = to_clk_frac(hw);
0051     unsigned long parent_rate = *prate;
0052     u32 div;
0053     u64 tmp, tmp_rate, result;
0054
0055     if (rate > parent_rate)
0056         return -EINVAL;
0057
0058     tmp = rate;
0059     tmp <<= frac->width;
0060     do_div(tmp, parent_rate);
0061     div = tmp;
0062
0063     if (!div)
0064         return -EINVAL;
0065
0066     tmp_rate = (u64)parent_rate * div;
0067     result = tmp_rate >> frac->width;
0068     if ((result << frac->width) < tmp_rate)
0069         result += 1;
0070     return result;
0071 }
0072
0073 static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate,
0074                  unsigned long parent_rate)
0075 {
0076     struct clk_frac *frac = to_clk_frac(hw);
0077     unsigned long flags;
0078     u32 div, val;
0079     u64 tmp;
0080
0081     if (rate > parent_rate)
0082         return -EINVAL;
0083
0084     tmp = rate;
0085     tmp <<= frac->width;
0086     do_div(tmp, parent_rate);
0087     div = tmp;
0088
0089     if (!div)
0090         return -EINVAL;
0091
0092     spin_lock_irqsave(&mxs_lock, flags);
0093
0094     val = readl_relaxed(frac->reg);
0095     val &= ~(((1 << frac->width) - 1) << frac->shift);
0096     val |= div << frac->shift;
0097     writel_relaxed(val, frac->reg);
0098
0099     spin_unlock_irqrestore(&mxs_lock, flags);
0100
0101     return mxs_clk_wait(frac->reg, frac->busy);
0102 }
0103
0104 static const struct clk_ops clk_frac_ops = {
0105     .recalc_rate = clk_frac_recalc_rate,
0106     .round_rate = clk_frac_round_rate,
0107     .set_rate = clk_frac_set_rate,
0108 };
0109
0110 struct clk *mxs_clk_frac(const char *name, const char *parent_name,
0111              void __iomem *reg, u8 shift, u8 width, u8 busy)
0112 {
0113     struct clk_frac *frac;
0114     struct clk *clk;
0115     struct clk_init_data init;
0116
0117     frac = kzalloc(sizeof(*frac), GFP_KERNEL);
0118     if (!frac)
0119         return ERR_PTR(-ENOMEM);
0120
0121     init.name = name;
0122     init.ops = &clk_frac_ops;
0123     init.flags = CLK_SET_RATE_PARENT;
0124     init.parent_names = (parent_name ? &parent_name: NULL);
0125     init.num_parents = (parent_name ? 1 : 0);
0126
0127     frac->reg = reg;
0128     frac->shift = shift;
0129     frac->width = width;
0130     frac->busy = busy;
0131     frac->hw.init = &init;
0132
0133     clk = clk_register(NULL, &frac->hw);
0134     if (IS_ERR(clk))
0135         kfree(frac);
0136
0137     return clk;
0138 }