clk/mvebu/orion.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Marvell Orion SoC clocks
0004  *
0005  * Copyright (C) 2014 Thomas Petazzoni
0006  *
0007  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0008  *
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/io.h>
0014 #include <linux/of.h>
0015 #include "common.h"
0016
0017 static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
0018     { .id = 0, .name = "ddrclk", }
0019 };
0020
0021 /*
0022  * Orion 5181
0023  */
0024
0025 #define SAR_MV88F5181_TCLK_FREQ      8
0026 #define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
0027
0028 static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
0029 {
0030     u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
0031         SAR_MV88F5181_TCLK_FREQ_MASK;
0032     if (opt == 0)
0033         return 133333333;
0034     else if (opt == 1)
0035         return 150000000;
0036     else if (opt == 2)
0037         return 166666667;
0038     else
0039         return 0;
0040 }
0041
0042 #define SAR_MV88F5181_CPU_FREQ       4
0043 #define SAR_MV88F5181_CPU_FREQ_MASK  0xf
0044
0045 static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
0046 {
0047     u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
0048         SAR_MV88F5181_CPU_FREQ_MASK;
0049     if (opt == 0)
0050         return 333333333;
0051     else if (opt == 1 || opt == 2)
0052         return 400000000;
0053     else if (opt == 3)
0054         return 500000000;
0055     else
0056         return 0;
0057 }
0058
0059 static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
0060                        int *mult, int *div)
0061 {
0062     u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
0063         SAR_MV88F5181_CPU_FREQ_MASK;
0064     if (opt == 0 || opt == 1) {
0065         *mult = 1;
0066         *div  = 2;
0067     } else if (opt == 2 || opt == 3) {
0068         *mult = 1;
0069         *div  = 3;
0070     } else {
0071         *mult = 0;
0072         *div  = 1;
0073     }
0074 }
0075
0076 static const struct coreclk_soc_desc mv88f5181_coreclks = {
0077     .get_tclk_freq = mv88f5181_get_tclk_freq,
0078     .get_cpu_freq = mv88f5181_get_cpu_freq,
0079     .get_clk_ratio = mv88f5181_get_clk_ratio,
0080     .ratios = orion_coreclk_ratios,
0081     .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
0082 };
0083
0084 static void __init mv88f5181_clk_init(struct device_node *np)
0085 {
0086     return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
0087 }
0088
0089 CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
0090
0091 /*
0092  * Orion 5182
0093  */
0094
0095 #define SAR_MV88F5182_TCLK_FREQ      8
0096 #define SAR_MV88F5182_TCLK_FREQ_MASK 0x3
0097
0098 static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar)
0099 {
0100     u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) &
0101         SAR_MV88F5182_TCLK_FREQ_MASK;
0102     if (opt == 1)
0103         return 150000000;
0104     else if (opt == 2)
0105         return 166666667;
0106     else
0107         return 0;
0108 }
0109
0110 #define SAR_MV88F5182_CPU_FREQ       4
0111 #define SAR_MV88F5182_CPU_FREQ_MASK  0xf
0112
0113 static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar)
0114 {
0115     u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
0116         SAR_MV88F5182_CPU_FREQ_MASK;
0117     if (opt == 0)
0118         return 333333333;
0119     else if (opt == 1 || opt == 2)
0120         return 400000000;
0121     else if (opt == 3)
0122         return 500000000;
0123     else
0124         return 0;
0125 }
0126
0127 static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id,
0128                        int *mult, int *div)
0129 {
0130     u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
0131         SAR_MV88F5182_CPU_FREQ_MASK;
0132     if (opt == 0 || opt == 1) {
0133         *mult = 1;
0134         *div  = 2;
0135     } else if (opt == 2 || opt == 3) {
0136         *mult = 1;
0137         *div  = 3;
0138     } else {
0139         *mult = 0;
0140         *div  = 1;
0141     }
0142 }
0143
0144 static const struct coreclk_soc_desc mv88f5182_coreclks = {
0145     .get_tclk_freq = mv88f5182_get_tclk_freq,
0146     .get_cpu_freq = mv88f5182_get_cpu_freq,
0147     .get_clk_ratio = mv88f5182_get_clk_ratio,
0148     .ratios = orion_coreclk_ratios,
0149     .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
0150 };
0151
0152 static void __init mv88f5182_clk_init(struct device_node *np)
0153 {
0154     return mvebu_coreclk_setup(np, &mv88f5182_coreclks);
0155 }
0156
0157 CLK_OF_DECLARE(mv88f5182_clk, "marvell,mv88f5182-core-clock", mv88f5182_clk_init);
0158
0159 /*
0160  * Orion 5281
0161  */
0162
0163 static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar)
0164 {
0165     /* On 5281, tclk is always 166 Mhz */
0166     return 166666667;
0167 }
0168
0169 #define SAR_MV88F5281_CPU_FREQ       4
0170 #define SAR_MV88F5281_CPU_FREQ_MASK  0xf
0171
0172 static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar)
0173 {
0174     u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
0175         SAR_MV88F5281_CPU_FREQ_MASK;
0176     if (opt == 1 || opt == 2)
0177         return 400000000;
0178     else if (opt == 3)
0179         return 500000000;
0180     else
0181         return 0;
0182 }
0183
0184 static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id,
0185                        int *mult, int *div)
0186 {
0187     u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
0188         SAR_MV88F5281_CPU_FREQ_MASK;
0189     if (opt == 1) {
0190         *mult = 1;
0191         *div = 2;
0192     } else if (opt == 2 || opt == 3) {
0193         *mult = 1;
0194         *div = 3;
0195     } else {
0196         *mult = 0;
0197         *div = 1;
0198     }
0199 }
0200
0201 static const struct coreclk_soc_desc mv88f5281_coreclks = {
0202     .get_tclk_freq = mv88f5281_get_tclk_freq,
0203     .get_cpu_freq = mv88f5281_get_cpu_freq,
0204     .get_clk_ratio = mv88f5281_get_clk_ratio,
0205     .ratios = orion_coreclk_ratios,
0206     .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
0207 };
0208
0209 static void __init mv88f5281_clk_init(struct device_node *np)
0210 {
0211     return mvebu_coreclk_setup(np, &mv88f5281_coreclks);
0212 }
0213
0214 CLK_OF_DECLARE(mv88f5281_clk, "marvell,mv88f5281-core-clock", mv88f5281_clk_init);
0215
0216 /*
0217  * Orion 6183
0218  */
0219
0220 #define SAR_MV88F6183_TCLK_FREQ      9
0221 #define SAR_MV88F6183_TCLK_FREQ_MASK 0x1
0222
0223 static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar)
0224 {
0225     u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) &
0226         SAR_MV88F6183_TCLK_FREQ_MASK;
0227     if (opt == 0)
0228         return 133333333;
0229     else if (opt == 1)
0230         return 166666667;
0231     else
0232         return 0;
0233 }
0234
0235 #define SAR_MV88F6183_CPU_FREQ       1
0236 #define SAR_MV88F6183_CPU_FREQ_MASK  0x3f
0237
0238 static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar)
0239 {
0240     u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
0241         SAR_MV88F6183_CPU_FREQ_MASK;
0242     if (opt == 9)
0243         return 333333333;
0244     else if (opt == 17)
0245         return 400000000;
0246     else
0247         return 0;
0248 }
0249
0250 static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id,
0251                        int *mult, int *div)
0252 {
0253     u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
0254         SAR_MV88F6183_CPU_FREQ_MASK;
0255     if (opt == 9 || opt == 17) {
0256         *mult = 1;
0257         *div  = 2;
0258     } else {
0259         *mult = 0;
0260         *div  = 1;
0261     }
0262 }
0263
0264 static const struct coreclk_soc_desc mv88f6183_coreclks = {
0265     .get_tclk_freq = mv88f6183_get_tclk_freq,
0266     .get_cpu_freq = mv88f6183_get_cpu_freq,
0267     .get_clk_ratio = mv88f6183_get_clk_ratio,
0268     .ratios = orion_coreclk_ratios,
0269     .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
0270 };
0271
0272
0273 static void __init mv88f6183_clk_init(struct device_node *np)
0274 {
0275     return mvebu_coreclk_setup(np, &mv88f6183_coreclks);
0276 }
0277
0278 CLK_OF_DECLARE(mv88f6183_clk, "marvell,mv88f6183-core-clock", mv88f6183_clk_init);