clk/mvebu/dove-divider.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Marvell Dove PMU Core PLL divider driver
0004  *
0005  * Cleaned up by substantially rewriting, and converted to DT by
0006  * Russell King.  Origin is not known.
0007  */
0008 #include <linux/clk-provider.h>
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014
0015 #include "dove-divider.h"
0016
0017 struct dove_clk {
0018     const char *name;
0019     struct clk_hw hw;
0020     void __iomem *base;
0021     spinlock_t *lock;
0022     u8 div_bit_start;
0023     u8 div_bit_end;
0024     u8 div_bit_load;
0025     u8 div_bit_size;
0026     u32 *divider_table;
0027 };
0028
0029 enum {
0030     DIV_CTRL0 = 0,
0031     DIV_CTRL1 = 4,
0032     DIV_CTRL1_N_RESET_MASK = BIT(10),
0033 };
0034
0035 #define to_dove_clk(hw) container_of(hw, struct dove_clk, hw)
0036
0037 static void dove_load_divider(void __iomem *base, u32 val, u32 mask, u32 load)
0038 {
0039     u32 v;
0040
0041     v = readl_relaxed(base + DIV_CTRL1) | DIV_CTRL1_N_RESET_MASK;
0042     writel_relaxed(v, base + DIV_CTRL1);
0043
0044     v = (readl_relaxed(base + DIV_CTRL0) & ~(mask | load)) | val;
0045     writel_relaxed(v, base + DIV_CTRL0);
0046     writel_relaxed(v | load, base + DIV_CTRL0);
0047     ndelay(250);
0048     writel_relaxed(v, base + DIV_CTRL0);
0049 }
0050
0051 static unsigned int dove_get_divider(struct dove_clk *dc)
0052 {
0053     unsigned int divider;
0054     u32 val;
0055
0056     val = readl_relaxed(dc->base + DIV_CTRL0);
0057     val >>= dc->div_bit_start;
0058
0059     divider = val & ~(~0 << dc->div_bit_size);
0060
0061     if (dc->divider_table)
0062         divider = dc->divider_table[divider];
0063
0064     return divider;
0065 }
0066
0067 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate,
0068                  unsigned long parent_rate, bool set)
0069 {
0070     unsigned int divider, max;
0071
0072     divider = DIV_ROUND_CLOSEST(parent_rate, rate);
0073
0074     if (dc->divider_table) {
0075         unsigned int i;
0076
0077         for (i = 0; dc->divider_table[i]; i++)
0078             if (divider == dc->divider_table[i]) {
0079                 divider = i;
0080                 break;
0081             }
0082
0083         if (!dc->divider_table[i])
0084             return -EINVAL;
0085     } else {
0086         max = 1 << dc->div_bit_size;
0087
0088         if (set && (divider == 0 || divider >= max))
0089             return -EINVAL;
0090         if (divider >= max)
0091             divider = max - 1;
0092         else if (divider == 0)
0093             divider = 1;
0094     }
0095
0096     return divider;
0097 }
0098
0099 static unsigned long dove_recalc_rate(struct clk_hw *hw, unsigned long parent)
0100 {
0101     struct dove_clk *dc = to_dove_clk(hw);
0102     unsigned int divider = dove_get_divider(dc);
0103     unsigned long rate = DIV_ROUND_CLOSEST(parent, divider);
0104
0105     pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
0106          __func__, dc->name, divider, parent, rate);
0107
0108     return rate;
0109 }
0110
0111 static long dove_round_rate(struct clk_hw *hw, unsigned long rate,
0112                 unsigned long *parent)
0113 {
0114     struct dove_clk *dc = to_dove_clk(hw);
0115     unsigned long parent_rate = *parent;
0116     int divider;
0117
0118     divider = dove_calc_divider(dc, rate, parent_rate, false);
0119     if (divider < 0)
0120         return divider;
0121
0122     rate = DIV_ROUND_CLOSEST(parent_rate, divider);
0123
0124     pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
0125          __func__, dc->name, divider, parent_rate, rate);
0126
0127     return rate;
0128 }
0129
0130 static int dove_set_clock(struct clk_hw *hw, unsigned long rate,
0131               unsigned long parent_rate)
0132 {
0133     struct dove_clk *dc = to_dove_clk(hw);
0134     u32 mask, load, div;
0135     int divider;
0136
0137     divider = dove_calc_divider(dc, rate, parent_rate, true);
0138     if (divider < 0)
0139         return divider;
0140
0141     pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
0142          __func__, dc->name, divider, parent_rate, rate);
0143
0144     div = (u32)divider << dc->div_bit_start;
0145     mask = ~(~0 << dc->div_bit_size) << dc->div_bit_start;
0146     load = BIT(dc->div_bit_load);
0147
0148     spin_lock(dc->lock);
0149     dove_load_divider(dc->base, div, mask, load);
0150     spin_unlock(dc->lock);
0151
0152     return 0;
0153 }
0154
0155 static const struct clk_ops dove_divider_ops = {
0156     .set_rate   = dove_set_clock,
0157     .round_rate = dove_round_rate,
0158     .recalc_rate    = dove_recalc_rate,
0159 };
0160
0161 static struct clk *clk_register_dove_divider(struct device *dev,
0162     struct dove_clk *dc, const char **parent_names, size_t num_parents,
0163     void __iomem *base)
0164 {
0165     char name[32];
0166     struct clk_init_data init = {
0167         .name = name,
0168         .ops = &dove_divider_ops,
0169         .parent_names = parent_names,
0170         .num_parents = num_parents,
0171     };
0172
0173     strlcpy(name, dc->name, sizeof(name));
0174
0175     dc->hw.init = &init;
0176     dc->base = base;
0177     dc->div_bit_size = dc->div_bit_end - dc->div_bit_start + 1;
0178
0179     return clk_register(dev, &dc->hw);
0180 }
0181
0182 static DEFINE_SPINLOCK(dove_divider_lock);
0183
0184 static u32 axi_divider[] = {-1, 2, 1, 3, 4, 6, 5, 7, 8, 10, 9, 0};
0185
0186 static struct dove_clk dove_hw_clocks[4] = {
0187     {
0188         .name = "axi",
0189         .lock = &dove_divider_lock,
0190         .div_bit_start = 1,
0191         .div_bit_end = 6,
0192         .div_bit_load = 7,
0193         .divider_table = axi_divider,
0194     }, {
0195         .name = "gpu",
0196         .lock = &dove_divider_lock,
0197         .div_bit_start = 8,
0198         .div_bit_end = 13,
0199         .div_bit_load = 14,
0200     }, {
0201         .name = "vmeta",
0202         .lock = &dove_divider_lock,
0203         .div_bit_start = 15,
0204         .div_bit_end = 20,
0205         .div_bit_load = 21,
0206     }, {
0207         .name = "lcd",
0208         .lock = &dove_divider_lock,
0209         .div_bit_start = 22,
0210         .div_bit_end = 27,
0211         .div_bit_load = 28,
0212     },
0213 };
0214
0215 static const char *core_pll[] = {
0216     "core-pll",
0217 };
0218
0219 static int dove_divider_init(struct device *dev, void __iomem *base,
0220     struct clk **clks)
0221 {
0222     struct clk *clk;
0223     int i;
0224
0225     /*
0226      * Create the core PLL clock.  We treat this as a fixed rate
0227      * clock as we don't know any better, and documentation is sparse.
0228      */
0229     clk = clk_register_fixed_rate(dev, core_pll[0], NULL, 0, 2000000000UL);
0230     if (IS_ERR(clk))
0231         return PTR_ERR(clk);
0232
0233     for (i = 0; i < ARRAY_SIZE(dove_hw_clocks); i++)
0234         clks[i] = clk_register_dove_divider(dev, &dove_hw_clocks[i],
0235                             core_pll,
0236                             ARRAY_SIZE(core_pll), base);
0237
0238     return 0;
0239 }
0240
0241 static struct clk *dove_divider_clocks[4];
0242
0243 static struct clk_onecell_data dove_divider_data = {
0244     .clks = dove_divider_clocks,
0245     .clk_num = ARRAY_SIZE(dove_divider_clocks),
0246 };
0247
0248 void __init dove_divider_clk_init(struct device_node *np)
0249 {
0250     void __iomem *base;
0251
0252     base = of_iomap(np, 0);
0253     if (WARN_ON(!base))
0254         return;
0255
0256     if (WARN_ON(dove_divider_init(NULL, base, dove_divider_clocks))) {
0257         iounmap(base);
0258         return;
0259     }
0260
0261     of_clk_add_provider(np, of_clk_src_onecell_get, &dove_divider_data);
0262 }