clk/mvebu/common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Marvell EBU SoC common clock handling
0004  *
0005  * Copyright (C) 2012 Marvell
0006  *
0007  * Gregory CLEMENT <gregory.clement@free-electrons.com>
0008  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0009  * Andrew Lunn <andrew@lunn.ch>
0010  *
0011  */
0012
0013 #ifndef __CLK_MVEBU_COMMON_H_
0014 #define __CLK_MVEBU_COMMON_H_
0015
0016 #include <linux/kernel.h>
0017
0018 extern spinlock_t ctrl_gating_lock;
0019
0020 struct device_node;
0021
0022 struct coreclk_ratio {
0023     int id;
0024     const char *name;
0025 };
0026
0027 struct coreclk_soc_desc {
0028     u32 (*get_tclk_freq)(void __iomem *sar);
0029     u32 (*get_cpu_freq)(void __iomem *sar);
0030     void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
0031     u32 (*get_refclk_freq)(void __iomem *sar);
0032     bool (*is_sscg_enabled)(void __iomem *sar);
0033     u32 (*fix_sscg_deviation)(u32 system_clk);
0034     const struct coreclk_ratio *ratios;
0035     int num_ratios;
0036 };
0037
0038 struct clk_gating_soc_desc {
0039     const char *name;
0040     const char *parent;
0041     int bit_idx;
0042     unsigned long flags;
0043 };
0044
0045 void __init mvebu_coreclk_setup(struct device_node *np,
0046                 const struct coreclk_soc_desc *desc);
0047
0048 void __init mvebu_clk_gating_setup(struct device_node *np,
0049                    const struct clk_gating_soc_desc *desc);
0050
0051 /*
0052  * This function is shared among the Kirkwood, Armada 370, Armada XP
0053  * and Armada 375 SoC
0054  */
0055 u32 kirkwood_fix_sscg_deviation(u32 system_clk);
0056 #endif