clk/mvebu/common.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Marvell EBU SoC common clock handling
0004  *
0005  * Copyright (C) 2012 Marvell
0006  *
0007  * Gregory CLEMENT <gregory.clement@free-electrons.com>
0008  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0009  * Andrew Lunn <andrew@lunn.ch>
0010  *
0011  */
0012
0013 #include <linux/kernel.h>
0014 #include <linux/slab.h>
0015 #include <linux/clk.h>
0016 #include <linux/clk-provider.h>
0017 #include <linux/io.h>
0018 #include <linux/of.h>
0019 #include <linux/of_address.h>
0020 #include <linux/syscore_ops.h>
0021
0022 #include "common.h"
0023
0024 /*
0025  * Core Clocks
0026  */
0027
0028 #define SSCG_CONF_MODE(reg) (((reg) >> 16) & 0x3)
0029 #define SSCG_SPREAD_DOWN    0x0
0030 #define SSCG_SPREAD_UP      0x1
0031 #define SSCG_SPREAD_CENTRAL 0x2
0032 #define SSCG_CONF_LOW(reg)  (((reg) >> 8) & 0xFF)
0033 #define SSCG_CONF_HIGH(reg) ((reg) & 0xFF)
0034
0035 static struct clk_onecell_data clk_data;
0036
0037 /*
0038  * This function can be used by the Kirkwood, the Armada 370, the
0039  * Armada XP and the Armada 375 SoC. The name of the function was
0040  * chosen following the dt convention: using the first known SoC
0041  * compatible with it.
0042  */
0043 u32 kirkwood_fix_sscg_deviation(u32 system_clk)
0044 {
0045     struct device_node *sscg_np = NULL;
0046     void __iomem *sscg_map;
0047     u32 sscg_reg;
0048     s32 low_bound, high_bound;
0049     u64 freq_swing_half;
0050
0051     sscg_np = of_find_node_by_name(NULL, "sscg");
0052     if (sscg_np == NULL) {
0053         pr_err("cannot get SSCG register node\n");
0054         return system_clk;
0055     }
0056
0057     sscg_map = of_iomap(sscg_np, 0);
0058     if (sscg_map == NULL) {
0059         pr_err("cannot map SSCG register\n");
0060         goto out;
0061     }
0062
0063     sscg_reg = readl(sscg_map);
0064     high_bound = SSCG_CONF_HIGH(sscg_reg);
0065     low_bound = SSCG_CONF_LOW(sscg_reg);
0066
0067     if ((high_bound - low_bound) <= 0)
0068         goto out;
0069     /*
0070      * From Marvell engineer we got the following formula (when
0071      * this code was written, the datasheet was erroneous)
0072      * Spread percentage = 1/96 * (H - L) / H
0073      * H = SSCG_High_Boundary
0074      * L = SSCG_Low_Boundary
0075      *
0076      * As the deviation is half of spread then it lead to the
0077      * following formula in the code.
0078      *
0079      * To avoid an overflow and not lose any significant digit in
0080      * the same time we have to use a 64 bit integer.
0081      */
0082
0083     freq_swing_half = (((u64)high_bound - (u64)low_bound)
0084             * (u64)system_clk);
0085     do_div(freq_swing_half, (2 * 96 * high_bound));
0086
0087     switch (SSCG_CONF_MODE(sscg_reg)) {
0088     case SSCG_SPREAD_DOWN:
0089         system_clk -= freq_swing_half;
0090         break;
0091     case SSCG_SPREAD_UP:
0092         system_clk += freq_swing_half;
0093         break;
0094     case SSCG_SPREAD_CENTRAL:
0095     default:
0096         break;
0097     }
0098
0099     iounmap(sscg_map);
0100
0101 out:
0102     of_node_put(sscg_np);
0103
0104     return system_clk;
0105 }
0106
0107 void __init mvebu_coreclk_setup(struct device_node *np,
0108                 const struct coreclk_soc_desc *desc)
0109 {
0110     const char *tclk_name = "tclk";
0111     const char *cpuclk_name = "cpuclk";
0112     void __iomem *base;
0113     unsigned long rate;
0114     int n;
0115
0116     base = of_iomap(np, 0);
0117     if (WARN_ON(!base))
0118         return;
0119
0120     /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
0121     clk_data.clk_num = 2 + desc->num_ratios;
0122
0123     /* One more clock for the optional refclk */
0124     if (desc->get_refclk_freq)
0125         clk_data.clk_num += 1;
0126
0127     clk_data.clks = kcalloc(clk_data.clk_num, sizeof(*clk_data.clks),
0128                 GFP_KERNEL);
0129     if (WARN_ON(!clk_data.clks)) {
0130         iounmap(base);
0131         return;
0132     }
0133
0134     /* Register TCLK */
0135     of_property_read_string_index(np, "clock-output-names", 0,
0136                       &tclk_name);
0137     rate = desc->get_tclk_freq(base);
0138     clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 0,
0139                            rate);
0140     WARN_ON(IS_ERR(clk_data.clks[0]));
0141
0142     /* Register CPU clock */
0143     of_property_read_string_index(np, "clock-output-names", 1,
0144                       &cpuclk_name);
0145     rate = desc->get_cpu_freq(base);
0146
0147     if (desc->is_sscg_enabled && desc->fix_sscg_deviation
0148         && desc->is_sscg_enabled(base))
0149         rate = desc->fix_sscg_deviation(rate);
0150
0151     clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 0,
0152                            rate);
0153     WARN_ON(IS_ERR(clk_data.clks[1]));
0154
0155     /* Register fixed-factor clocks derived from CPU clock */
0156     for (n = 0; n < desc->num_ratios; n++) {
0157         const char *rclk_name = desc->ratios[n].name;
0158         int mult, div;
0159
0160         of_property_read_string_index(np, "clock-output-names",
0161                           2+n, &rclk_name);
0162         desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
0163         clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
0164                        cpuclk_name, 0, mult, div);
0165         WARN_ON(IS_ERR(clk_data.clks[2+n]));
0166     }
0167
0168     /* Register optional refclk */
0169     if (desc->get_refclk_freq) {
0170         const char *name = "refclk";
0171         of_property_read_string_index(np, "clock-output-names",
0172                           2 + desc->num_ratios, &name);
0173         rate = desc->get_refclk_freq(base);
0174         clk_data.clks[2 + desc->num_ratios] =
0175             clk_register_fixed_rate(NULL, name, NULL, 0, rate);
0176         WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
0177     }
0178
0179     /* SAR register isn't needed anymore */
0180     iounmap(base);
0181
0182     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
0183 }
0184
0185 /*
0186  * Clock Gating Control
0187  */
0188
0189 DEFINE_SPINLOCK(ctrl_gating_lock);
0190
0191 struct clk_gating_ctrl {
0192     spinlock_t *lock;
0193     struct clk **gates;
0194     int num_gates;
0195     void __iomem *base;
0196     u32 saved_reg;
0197 };
0198
0199 static struct clk_gating_ctrl *ctrl;
0200
0201 static struct clk *clk_gating_get_src(
0202     struct of_phandle_args *clkspec, void *data)
0203 {
0204     int n;
0205
0206     if (clkspec->args_count < 1)
0207         return ERR_PTR(-EINVAL);
0208
0209     for (n = 0; n < ctrl->num_gates; n++) {
0210         struct clk_gate *gate =
0211             to_clk_gate(__clk_get_hw(ctrl->gates[n]));
0212         if (clkspec->args[0] == gate->bit_idx)
0213             return ctrl->gates[n];
0214     }
0215     return ERR_PTR(-ENODEV);
0216 }
0217
0218 static int mvebu_clk_gating_suspend(void)
0219 {
0220     ctrl->saved_reg = readl(ctrl->base);
0221     return 0;
0222 }
0223
0224 static void mvebu_clk_gating_resume(void)
0225 {
0226     writel(ctrl->saved_reg, ctrl->base);
0227 }
0228
0229 static struct syscore_ops clk_gate_syscore_ops = {
0230     .suspend = mvebu_clk_gating_suspend,
0231     .resume = mvebu_clk_gating_resume,
0232 };
0233
0234 void __init mvebu_clk_gating_setup(struct device_node *np,
0235                    const struct clk_gating_soc_desc *desc)
0236 {
0237     struct clk *clk;
0238     void __iomem *base;
0239     const char *default_parent = NULL;
0240     int n;
0241
0242     if (ctrl) {
0243         pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n");
0244         return;
0245     }
0246
0247     base = of_iomap(np, 0);
0248     if (WARN_ON(!base))
0249         return;
0250
0251     clk = of_clk_get(np, 0);
0252     if (!IS_ERR(clk)) {
0253         default_parent = __clk_get_name(clk);
0254         clk_put(clk);
0255     }
0256
0257     ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
0258     if (WARN_ON(!ctrl))
0259         goto ctrl_out;
0260
0261     /* lock must already be initialized */
0262     ctrl->lock = &ctrl_gating_lock;
0263
0264     ctrl->base = base;
0265
0266     /* Count, allocate, and register clock gates */
0267     for (n = 0; desc[n].name;)
0268         n++;
0269
0270     ctrl->num_gates = n;
0271     ctrl->gates = kcalloc(ctrl->num_gates, sizeof(*ctrl->gates),
0272                   GFP_KERNEL);
0273     if (WARN_ON(!ctrl->gates))
0274         goto gates_out;
0275
0276     for (n = 0; n < ctrl->num_gates; n++) {
0277         const char *parent =
0278             (desc[n].parent) ? desc[n].parent : default_parent;
0279         ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
0280                     desc[n].flags, base, desc[n].bit_idx,
0281                     0, ctrl->lock);
0282         WARN_ON(IS_ERR(ctrl->gates[n]));
0283     }
0284
0285     of_clk_add_provider(np, clk_gating_get_src, ctrl);
0286
0287     register_syscore_ops(&clk_gate_syscore_ops);
0288
0289     return;
0290 gates_out:
0291     kfree(ctrl);
0292 ctrl_out:
0293     iounmap(base);
0294 }