clk/mvebu/armada-38x.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Marvell Armada 380/385 SoC clocks
0004  *
0005  * Copyright (C) 2014 Marvell
0006  *
0007  * Gregory CLEMENT <gregory.clement@free-electrons.com>
0008  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0009  * Andrew Lunn <andrew@lunn.ch>
0010  *
0011  */
0012
0013 #include <linux/kernel.h>
0014 #include <linux/clk-provider.h>
0015 #include <linux/io.h>
0016 #include <linux/of.h>
0017 #include "common.h"
0018
0019 /*
0020  * SAR[14:10] : Ratios between PCLK0, NBCLK, HCLK and DRAM clocks
0021  *
0022  * SAR[15]    : TCLK frequency
0023  *       0 = 250 MHz
0024  *       1 = 200 MHz
0025  */
0026
0027 #define SAR_A380_TCLK_FREQ_OPT        15
0028 #define SAR_A380_TCLK_FREQ_OPT_MASK   0x1
0029 #define SAR_A380_CPU_DDR_L2_FREQ_OPT      10
0030 #define SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
0031
0032 static const u32 armada_38x_tclk_frequencies[] __initconst = {
0033     250000000,
0034     200000000,
0035 };
0036
0037 static u32 __init armada_38x_get_tclk_freq(void __iomem *sar)
0038 {
0039     u8 tclk_freq_select;
0040
0041     tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) &
0042                 SAR_A380_TCLK_FREQ_OPT_MASK);
0043     return armada_38x_tclk_frequencies[tclk_freq_select];
0044 }
0045
0046 static const u32 armada_38x_cpu_frequencies[] __initconst = {
0047     666 * 1000 * 1000,  0, 800 * 1000 * 1000, 0,
0048     1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
0049     1332 * 1000 * 1000, 0, 0, 0,
0050     1600 * 1000 * 1000, 0, 0, 0,
0051     1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
0052 };
0053
0054 static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
0055 {
0056     u8 cpu_freq_select;
0057
0058     cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
0059                SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
0060     if (cpu_freq_select >= ARRAY_SIZE(armada_38x_cpu_frequencies)) {
0061         pr_err("Selected CPU frequency (%d) unsupported\n",
0062             cpu_freq_select);
0063         return 0;
0064     }
0065
0066     return armada_38x_cpu_frequencies[cpu_freq_select];
0067 }
0068
0069 enum { A380_CPU_TO_DDR, A380_CPU_TO_L2 };
0070
0071 static const struct coreclk_ratio armada_38x_coreclk_ratios[] __initconst = {
0072     { .id = A380_CPU_TO_L2,  .name = "l2clk" },
0073     { .id = A380_CPU_TO_DDR, .name = "ddrclk" },
0074 };
0075
0076 static const int armada_38x_cpu_l2_ratios[32][2] __initconst = {
0077     {1, 2}, {0, 1}, {1, 2}, {0, 1},
0078     {1, 2}, {0, 1}, {1, 2}, {0, 1},
0079     {1, 2}, {0, 1}, {0, 1}, {0, 1},
0080     {1, 2}, {0, 1}, {0, 1}, {0, 1},
0081     {1, 2}, {0, 1}, {0, 1}, {1, 2},
0082     {0, 1}, {0, 1}, {0, 1}, {0, 1},
0083     {0, 1}, {0, 1}, {0, 1}, {0, 1},
0084     {0, 1}, {0, 1}, {0, 1}, {0, 1},
0085 };
0086
0087 static const int armada_38x_cpu_ddr_ratios[32][2] __initconst = {
0088     {0, 1}, {0, 1}, {0, 1}, {0, 1},
0089     {1, 2}, {0, 1}, {0, 1}, {0, 1},
0090     {1, 2}, {0, 1}, {0, 1}, {0, 1},
0091     {1, 2}, {0, 1}, {0, 1}, {0, 1},
0092     {1, 2}, {0, 1}, {0, 1}, {7, 15},
0093     {0, 1}, {0, 1}, {0, 1}, {0, 1},
0094     {0, 1}, {0, 1}, {0, 1}, {0, 1},
0095     {0, 1}, {0, 1}, {0, 1}, {0, 1},
0096 };
0097
0098 static void __init armada_38x_get_clk_ratio(
0099     void __iomem *sar, int id, int *mult, int *div)
0100 {
0101     u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
0102         SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
0103
0104     switch (id) {
0105     case A380_CPU_TO_L2:
0106         *mult = armada_38x_cpu_l2_ratios[opt][0];
0107         *div = armada_38x_cpu_l2_ratios[opt][1];
0108         break;
0109     case A380_CPU_TO_DDR:
0110         *mult = armada_38x_cpu_ddr_ratios[opt][0];
0111         *div = armada_38x_cpu_ddr_ratios[opt][1];
0112         break;
0113     }
0114 }
0115
0116 static const struct coreclk_soc_desc armada_38x_coreclks = {
0117     .get_tclk_freq = armada_38x_get_tclk_freq,
0118     .get_cpu_freq = armada_38x_get_cpu_freq,
0119     .get_clk_ratio = armada_38x_get_clk_ratio,
0120     .ratios = armada_38x_coreclk_ratios,
0121     .num_ratios = ARRAY_SIZE(armada_38x_coreclk_ratios),
0122 };
0123
0124 static void __init armada_38x_coreclk_init(struct device_node *np)
0125 {
0126     mvebu_coreclk_setup(np, &armada_38x_coreclks);
0127 }
0128 CLK_OF_DECLARE(armada_38x_core_clk, "marvell,armada-380-core-clock",
0129            armada_38x_coreclk_init);
0130
0131 /*
0132  * Clock Gating Control
0133  */
0134 static const struct clk_gating_soc_desc armada_38x_gating_desc[] __initconst = {
0135     { "audio", NULL, 0 },
0136     { "ge2", NULL, 2 },
0137     { "ge1", NULL, 3 },
0138     { "ge0", NULL, 4 },
0139     { "pex1", NULL, 5 },
0140     { "pex2", NULL, 6 },
0141     { "pex3", NULL, 7 },
0142     { "pex0", NULL, 8 },
0143     { "usb3h0", NULL, 9 },
0144     { "usb3h1", NULL, 10 },
0145     { "usb3d", NULL, 11 },
0146     { "bm", NULL, 13 },
0147     { "crypto0z", NULL, 14 },
0148     { "sata0", NULL, 15 },
0149     { "crypto1z", NULL, 16 },
0150     { "sdio", NULL, 17 },
0151     { "usb2", NULL, 18 },
0152     { "crypto1", NULL, 21 },
0153     { "xor0", NULL, 22 },
0154     { "crypto0", NULL, 23 },
0155     { "tdm", NULL, 25 },
0156     { "xor1", NULL, 28 },
0157     { "sata1", NULL, 30 },
0158     { }
0159 };
0160
0161 static void __init armada_38x_clk_gating_init(struct device_node *np)
0162 {
0163     mvebu_clk_gating_setup(np, armada_38x_gating_desc);
0164 }
0165 CLK_OF_DECLARE(armada_38x_clk_gating, "marvell,armada-380-gating-clock",
0166            armada_38x_clk_gating_init);