clk/mvebu/armada-37xx-tbg.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Marvell Armada 37xx SoC Time Base Generator clocks
0004  *
0005  * Copyright (C) 2016 Marvell
0006  *
0007  * Gregory CLEMENT <gregory.clement@free-electrons.com>
0008  */
0009
0010 #include <linux/clk-provider.h>
0011 #include <linux/clk.h>
0012 #include <linux/io.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/slab.h>
0017
0018 #define NUM_TBG     4
0019
0020 #define TBG_CTRL0       0x4
0021 #define TBG_CTRL1       0x8
0022 #define TBG_CTRL7       0x20
0023 #define TBG_CTRL8       0x30
0024
0025 #define TBG_DIV_MASK        0x1FF
0026
0027 #define TBG_A_REFDIV        0
0028 #define TBG_B_REFDIV        16
0029
0030 #define TBG_A_FBDIV     2
0031 #define TBG_B_FBDIV     18
0032
0033 #define TBG_A_VCODIV_SE     0
0034 #define TBG_B_VCODIV_SE     16
0035
0036 #define TBG_A_VCODIV_DIFF   1
0037 #define TBG_B_VCODIV_DIFF   17
0038
0039 struct tbg_def {
0040     char *name;
0041     u32 refdiv_offset;
0042     u32 fbdiv_offset;
0043     u32 vcodiv_reg;
0044     u32 vcodiv_offset;
0045 };
0046
0047 static const struct tbg_def tbg[NUM_TBG] = {
0048     {"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF},
0049     {"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8, TBG_B_VCODIV_DIFF},
0050     {"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SE},
0051     {"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SE},
0052 };
0053
0054 static unsigned int tbg_get_mult(void __iomem *reg, const struct tbg_def *ptbg)
0055 {
0056     u32 val;
0057
0058     val = readl(reg + TBG_CTRL0);
0059
0060     return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2;
0061 }
0062
0063 static unsigned int tbg_get_div(void __iomem *reg, const struct tbg_def *ptbg)
0064 {
0065     u32 val;
0066     unsigned int div;
0067
0068     val = readl(reg + TBG_CTRL7);
0069
0070     div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK;
0071     if (div == 0)
0072         div = 1;
0073     val = readl(reg + ptbg->vcodiv_reg);
0074
0075     div *= 1 << ((val >>  ptbg->vcodiv_offset) & TBG_DIV_MASK);
0076
0077     return div;
0078 }
0079
0080
0081 static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
0082 {
0083     struct device_node *np = pdev->dev.of_node;
0084     struct clk_hw_onecell_data *hw_tbg_data;
0085     struct device *dev = &pdev->dev;
0086     const char *parent_name;
0087     struct resource *res;
0088     struct clk *parent;
0089     void __iomem *reg;
0090     int i, ret;
0091
0092     hw_tbg_data = devm_kzalloc(&pdev->dev,
0093                    struct_size(hw_tbg_data, hws, NUM_TBG),
0094                    GFP_KERNEL);
0095     if (!hw_tbg_data)
0096         return -ENOMEM;
0097     hw_tbg_data->num = NUM_TBG;
0098     platform_set_drvdata(pdev, hw_tbg_data);
0099
0100     parent = clk_get(dev, NULL);
0101     if (IS_ERR(parent)) {
0102         dev_err(dev, "Could get the clock parent\n");
0103         return -EINVAL;
0104     }
0105     parent_name = __clk_get_name(parent);
0106     clk_put(parent);
0107
0108     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0109     reg = devm_ioremap_resource(dev, res);
0110     if (IS_ERR(reg))
0111         return PTR_ERR(reg);
0112
0113     for (i = 0; i < NUM_TBG; i++) {
0114         const char *name;
0115         unsigned int mult, div;
0116
0117         name = tbg[i].name;
0118         mult = tbg_get_mult(reg, &tbg[i]);
0119         div = tbg_get_div(reg, &tbg[i]);
0120         hw_tbg_data->hws[i] = clk_hw_register_fixed_factor(NULL, name,
0121                         parent_name, 0, mult, div);
0122         if (IS_ERR(hw_tbg_data->hws[i]))
0123             dev_err(dev, "Can't register TBG clock %s\n", name);
0124     }
0125
0126     ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, hw_tbg_data);
0127
0128     return ret;
0129 }
0130
0131 static int armada_3700_tbg_clock_remove(struct platform_device *pdev)
0132 {
0133     int i;
0134     struct clk_hw_onecell_data *hw_tbg_data = platform_get_drvdata(pdev);
0135
0136     of_clk_del_provider(pdev->dev.of_node);
0137     for (i = 0; i < hw_tbg_data->num; i++)
0138         clk_hw_unregister_fixed_factor(hw_tbg_data->hws[i]);
0139
0140     return 0;
0141 }
0142
0143 static const struct of_device_id armada_3700_tbg_clock_of_match[] = {
0144     { .compatible = "marvell,armada-3700-tbg-clock", },
0145     { }
0146 };
0147
0148 static struct platform_driver armada_3700_tbg_clock_driver = {
0149     .probe = armada_3700_tbg_clock_probe,
0150     .remove = armada_3700_tbg_clock_remove,
0151     .driver     = {
0152         .name   = "marvell-armada-3700-tbg-clock",
0153         .of_match_table = armada_3700_tbg_clock_of_match,
0154     },
0155 };
0156
0157 builtin_platform_driver(armada_3700_tbg_clock_driver);