clk/microchip/clk-pic32mzda.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Purna Chandra Mandal,<purna.mandal@microchip.com>
0004  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
0005  */
0006 #include <dt-bindings/clock/microchip,pic32-clock.h>
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/clkdev.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/platform_device.h>
0015 #include <asm/traps.h>
0016
0017 #include "clk-core.h"
0018
0019 /* FRC Postscaler */
0020 #define OSC_FRCDIV_MASK     0x07
0021 #define OSC_FRCDIV_SHIFT    24
0022
0023 /* SPLL fields */
0024 #define PLL_ICLK_MASK       0x01
0025 #define PLL_ICLK_SHIFT      7
0026
0027 #define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags)    \
0028     {                           \
0029         .ctrl_reg = (__reg),                \
0030         .init_data = {                  \
0031             .name = (__clk_name),           \
0032             .parent_names = (const char *[]) {  \
0033                 "sys_clk"           \
0034             },                  \
0035             .num_parents = 1,           \
0036             .ops = &pic32_pbclk_ops,        \
0037             .flags = (__flags),         \
0038         },                      \
0039     }
0040
0041 #define DECLARE_REFO_CLOCK(__clkid, __reg)              \
0042     {                               \
0043         .ctrl_reg = (__reg),                    \
0044         .init_data = {                      \
0045             .name = "refo" #__clkid "_clk",         \
0046             .parent_names = (const char *[]) {      \
0047                 "sys_clk", "pb1_clk", "posc_clk",   \
0048                 "frc_clk", "lprc_clk", "sosc_clk",  \
0049                 "sys_pll", "refi" #__clkid "_clk",  \
0050                 "bfrc_clk",             \
0051             },                      \
0052             .num_parents = 9,               \
0053             .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\
0054             .ops = &pic32_roclk_ops,            \
0055         },                          \
0056         .parent_map = (const u32[]) {               \
0057             0, 1, 2, 3, 4, 5, 7, 8, 9           \
0058         },                          \
0059     }
0060
0061 static const struct pic32_ref_osc_data ref_clks[] = {
0062     DECLARE_REFO_CLOCK(1, 0x80),
0063     DECLARE_REFO_CLOCK(2, 0xa0),
0064     DECLARE_REFO_CLOCK(3, 0xc0),
0065     DECLARE_REFO_CLOCK(4, 0xe0),
0066     DECLARE_REFO_CLOCK(5, 0x100),
0067 };
0068
0069 static const struct pic32_periph_clk_data periph_clocks[] = {
0070     DECLARE_PERIPHERAL_CLOCK("pb1_clk", 0x140, 0),
0071     DECLARE_PERIPHERAL_CLOCK("pb2_clk", 0x150, CLK_IGNORE_UNUSED),
0072     DECLARE_PERIPHERAL_CLOCK("pb3_clk", 0x160, 0),
0073     DECLARE_PERIPHERAL_CLOCK("pb4_clk", 0x170, 0),
0074     DECLARE_PERIPHERAL_CLOCK("pb5_clk", 0x180, 0),
0075     DECLARE_PERIPHERAL_CLOCK("pb6_clk", 0x190, 0),
0076     DECLARE_PERIPHERAL_CLOCK("cpu_clk", 0x1a0, CLK_IGNORE_UNUSED),
0077 };
0078
0079 static const struct pic32_sys_clk_data sys_mux_clk = {
0080     .slew_reg = 0x1c0,
0081     .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
0082     .init_data = {
0083         .name = "sys_clk",
0084         .parent_names = (const char *[]) {
0085             "frcdiv_clk", "sys_pll", "posc_clk",
0086             "sosc_clk", "lprc_clk", "frcdiv_clk",
0087         },
0088         .num_parents = 6,
0089         .ops = &pic32_sclk_ops,
0090     },
0091     .parent_map = (const u32[]) {
0092         0, 1, 2, 4, 5, 7,
0093     },
0094 };
0095
0096 static const struct pic32_sys_pll_data sys_pll = {
0097     .ctrl_reg = 0x020,
0098     .status_reg = 0x1d0,
0099     .lock_mask = BIT(7),
0100     .init_data = {
0101         .name = "sys_pll",
0102         .parent_names = (const char *[]) {
0103             "spll_mux_clk"
0104         },
0105         .num_parents = 1,
0106         .ops = &pic32_spll_ops,
0107     },
0108 };
0109
0110 static const struct pic32_sec_osc_data sosc_clk = {
0111     .status_reg = 0x1d0,
0112     .enable_mask = BIT(1),
0113     .status_mask = BIT(4),
0114     .fixed_rate = 32768,
0115     .init_data = {
0116         .name = "sosc_clk",
0117         .parent_names = NULL,
0118         .ops = &pic32_sosc_ops,
0119     },
0120 };
0121
0122 static int pic32mzda_critical_clks[] = {
0123     PB2CLK, PB7CLK
0124 };
0125
0126 /* PIC32MZDA clock data */
0127 struct pic32mzda_clk_data {
0128     struct clk *clks[MAXCLKS];
0129     struct pic32_clk_common core;
0130     struct clk_onecell_data onecell_data;
0131     struct notifier_block failsafe_notifier;
0132 };
0133
0134 static int pic32_fscm_nmi(struct notifier_block *nb,
0135               unsigned long action, void *data)
0136 {
0137     struct pic32mzda_clk_data *cd;
0138
0139     cd  = container_of(nb, struct pic32mzda_clk_data, failsafe_notifier);
0140
0141     /* SYSCLK is now running from BFRCCLK. Report clock failure. */
0142     if (readl(cd->core.iobase) & BIT(2))
0143         pr_alert("pic32-clk: FSCM detected clk failure.\n");
0144
0145     /* TODO: detect reason of failure and recover accordingly */
0146
0147     return NOTIFY_OK;
0148 }
0149
0150 static int pic32mzda_clk_probe(struct platform_device *pdev)
0151 {
0152     const char *const pll_mux_parents[] = {"posc_clk", "frc_clk"};
0153     struct device_node *np = pdev->dev.of_node;
0154     struct pic32mzda_clk_data *cd;
0155     struct pic32_clk_common *core;
0156     struct clk *pll_mux_clk, *clk;
0157     struct clk **clks;
0158     int nr_clks, i, ret;
0159
0160     cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL);
0161     if (!cd)
0162         return -ENOMEM;
0163
0164     core = &cd->core;
0165     core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np));
0166     if (IS_ERR(core->iobase)) {
0167         dev_err(&pdev->dev, "pic32-clk: failed to map registers\n");
0168         return PTR_ERR(core->iobase);
0169     }
0170
0171     spin_lock_init(&core->reg_lock);
0172     core->dev = &pdev->dev;
0173     clks = &cd->clks[0];
0174
0175     /* register fixed rate clocks */
0176     clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,
0177                         0, 24000000);
0178     clks[FRCCLK] =  clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,
0179                         0, 8000000);
0180     clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,
0181                         0, 8000000);
0182     clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,
0183                         0, 32000);
0184     clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,
0185                         0, 24000000);
0186     /* fixed rate (optional) clock */
0187     if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) {
0188         pr_info("pic32-clk: dt requests SOSC.\n");
0189         clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core);
0190     }
0191     /* divider clock */
0192     clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
0193                            "frc_clk", 0,
0194                            core->iobase,
0195                            OSC_FRCDIV_SHIFT,
0196                            OSC_FRCDIV_MASK,
0197                            CLK_DIVIDER_POWER_OF_TWO,
0198                            &core->reg_lock);
0199     /* PLL ICLK mux */
0200     pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",
0201                        pll_mux_parents, 2, 0,
0202                        core->iobase + 0x020,
0203                        PLL_ICLK_SHIFT, 1, 0, &core->reg_lock);
0204     if (IS_ERR(pll_mux_clk))
0205         pr_err("spll_mux_clk: clk register failed\n");
0206
0207     /* PLL */
0208     clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core);
0209     /* SYSTEM clock */
0210     clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core);
0211     /* Peripheral bus clocks */
0212     for (nr_clks = PB1CLK, i = 0; nr_clks <= PB7CLK; i++, nr_clks++)
0213         clks[nr_clks] = pic32_periph_clk_register(&periph_clocks[i],
0214                               core);
0215     /* Reference oscillator clock */
0216     for (nr_clks = REF1CLK, i = 0; nr_clks <= REF5CLK; i++, nr_clks++)
0217         clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core);
0218
0219     /* register clkdev */
0220     for (i = 0; i < MAXCLKS; i++) {
0221         if (IS_ERR(clks[i]))
0222             continue;
0223         clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i]));
0224     }
0225
0226     /* register clock provider */
0227     cd->onecell_data.clks = clks;
0228     cd->onecell_data.clk_num = MAXCLKS;
0229     ret = of_clk_add_provider(np, of_clk_src_onecell_get,
0230                   &cd->onecell_data);
0231     if (ret)
0232         return ret;
0233
0234     /* force enable critical clocks */
0235     for (i = 0; i < ARRAY_SIZE(pic32mzda_critical_clks); i++) {
0236         clk = clks[pic32mzda_critical_clks[i]];
0237         if (clk_prepare_enable(clk))
0238             dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n",
0239                 __clk_get_name(clk));
0240     }
0241
0242     /* register NMI for failsafe clock monitor */
0243     cd->failsafe_notifier.notifier_call = pic32_fscm_nmi;
0244     return register_nmi_notifier(&cd->failsafe_notifier);
0245 }
0246
0247 static const struct of_device_id pic32mzda_clk_match_table[] = {
0248     { .compatible = "microchip,pic32mzda-clk", },
0249     { }
0250 };
0251 MODULE_DEVICE_TABLE(of, pic32mzda_clk_match_table);
0252
0253 static struct platform_driver pic32mzda_clk_driver = {
0254     .probe      = pic32mzda_clk_probe,
0255     .driver     = {
0256         .name   = "clk-pic32mzda",
0257         .of_match_table = pic32mzda_clk_match_table,
0258     },
0259 };
0260
0261 static int __init microchip_pic32mzda_clk_init(void)
0262 {
0263     return platform_driver_register(&pic32mzda_clk_driver);
0264 }
0265 core_initcall(microchip_pic32mzda_clk_init);
0266
0267 MODULE_DESCRIPTION("Microchip PIC32MZDA Clock Driver");
0268 MODULE_LICENSE("GPL v2");
0269 MODULE_ALIAS("platform:clk-pic32mzda");