clk/meson/meson8b.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2015 Endless Mobile, Inc.
0004  * Author: Carlo Caione <carlo@endlessm.com>
0005  *
0006  * Copyright (c) 2016 BayLibre, Inc.
0007  * Michael Turquette <mturquette@baylibre.com>
0008  */
0009
0010 #ifndef __MESON8B_H
0011 #define __MESON8B_H
0012
0013 /*
0014  * Clock controller register offsets
0015  *
0016  * Register offsets from the HardKernel[0] data sheet are listed in comment
0017  * blocks below. Those offsets must be multiplied by 4 before adding them to
0018  * the base address to get the right value
0019  *
0020  * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
0021  */
0022 #define HHI_GP_PLL_CNTL         0x40  /* 0x10 offset in data sheet */
0023 #define HHI_GP_PLL_CNTL2        0x44  /* 0x11 offset in data sheet */
0024 #define HHI_GP_PLL_CNTL3        0x48  /* 0x12 offset in data sheet */
0025 #define HHI_GP_PLL_CNTL4        0x4C  /* 0x13 offset in data sheet */
0026 #define HHI_GP_PLL_CNTL5        0x50  /* 0x14 offset in data sheet */
0027 #define HHI_VIID_CLK_DIV        0x128 /* 0x4a offset in data sheet */
0028 #define HHI_VIID_CLK_CNTL       0x12c /* 0x4b offset in data sheet */
0029 #define HHI_GCLK_MPEG0          0x140 /* 0x50 offset in data sheet */
0030 #define HHI_GCLK_MPEG1          0x144 /* 0x51 offset in data sheet */
0031 #define HHI_GCLK_MPEG2          0x148 /* 0x52 offset in data sheet */
0032 #define HHI_GCLK_OTHER          0x150 /* 0x54 offset in data sheet */
0033 #define HHI_GCLK_AO         0x154 /* 0x55 offset in data sheet */
0034 #define HHI_SYS_CPU_CLK_CNTL1       0x15c /* 0x57 offset in data sheet */
0035 #define HHI_VID_CLK_DIV         0x164 /* 0x59 offset in data sheet */
0036 #define HHI_MPEG_CLK_CNTL       0x174 /* 0x5d offset in data sheet */
0037 #define HHI_AUD_CLK_CNTL        0x178 /* 0x5e offset in data sheet */
0038 #define HHI_VID_CLK_CNTL        0x17c /* 0x5f offset in data sheet */
0039 #define HHI_AUD_CLK_CNTL2       0x190 /* 0x64 offset in data sheet */
0040 #define HHI_VID_CLK_CNTL2       0x194 /* 0x65 offset in data sheet */
0041 #define HHI_VID_DIVIDER_CNTL        0x198 /* 0x66 offset in data sheet */
0042 #define HHI_SYS_CPU_CLK_CNTL0       0x19c /* 0x67 offset in data sheet */
0043 #define HHI_MALI_CLK_CNTL       0x1b0 /* 0x6c offset in data sheet */
0044 #define HHI_VPU_CLK_CNTL        0x1bc /* 0x6f offset in data sheet */
0045 #define HHI_HDMI_CLK_CNTL       0x1cc /* 0x73 offset in data sheet */
0046 #define HHI_VDEC_CLK_CNTL       0x1e0 /* 0x78 offset in data sheet */
0047 #define HHI_VDEC2_CLK_CNTL      0x1e4 /* 0x79 offset in data sheet */
0048 #define HHI_VDEC3_CLK_CNTL      0x1e8 /* 0x7a offset in data sheet */
0049 #define HHI_NAND_CLK_CNTL       0x25c /* 0x97 offset in data sheet */
0050 #define HHI_MPLL_CNTL           0x280 /* 0xa0 offset in data sheet */
0051 #define HHI_SYS_PLL_CNTL        0x300 /* 0xc0 offset in data sheet */
0052 #define HHI_VID_PLL_CNTL        0x320 /* 0xc8 offset in data sheet */
0053 #define HHI_VID_PLL_CNTL2       0x324 /* 0xc9 offset in data sheet */
0054 #define HHI_VID_PLL_CNTL3       0x328 /* 0xca offset in data sheet */
0055 #define HHI_VID_PLL_CNTL4       0x32c /* 0xcb offset in data sheet */
0056 #define HHI_VID_PLL_CNTL5       0x330 /* 0xcc offset in data sheet */
0057 #define HHI_VID_PLL_CNTL6       0x334 /* 0xcd offset in data sheet */
0058 #define HHI_VID2_PLL_CNTL       0x380 /* 0xe0 offset in data sheet */
0059 #define HHI_VID2_PLL_CNTL2      0x384 /* 0xe1 offset in data sheet */
0060 #define HHI_VID2_PLL_CNTL3      0x388 /* 0xe2 offset in data sheet */
0061 #define HHI_VID2_PLL_CNTL4      0x38c /* 0xe3 offset in data sheet */
0062 #define HHI_VID2_PLL_CNTL5      0x390 /* 0xe4 offset in data sheet */
0063 #define HHI_VID2_PLL_CNTL6      0x394 /* 0xe5 offset in data sheet */
0064
0065 /*
0066  * MPLL register offeset taken from the S905 datasheet. Vendor kernel source
0067  * confirm these are the same for the S805.
0068  */
0069 #define HHI_MPLL_CNTL           0x280 /* 0xa0 offset in data sheet */
0070 #define HHI_MPLL_CNTL2          0x284 /* 0xa1 offset in data sheet */
0071 #define HHI_MPLL_CNTL3          0x288 /* 0xa2 offset in data sheet */
0072 #define HHI_MPLL_CNTL4          0x28C /* 0xa3 offset in data sheet */
0073 #define HHI_MPLL_CNTL5          0x290 /* 0xa4 offset in data sheet */
0074 #define HHI_MPLL_CNTL6          0x294 /* 0xa5 offset in data sheet */
0075 #define HHI_MPLL_CNTL7          0x298 /* 0xa6 offset in data sheet */
0076 #define HHI_MPLL_CNTL8          0x29C /* 0xa7 offset in data sheet */
0077 #define HHI_MPLL_CNTL9          0x2A0 /* 0xa8 offset in data sheet */
0078 #define HHI_MPLL_CNTL10         0x2A4 /* 0xa9 offset in data sheet */
0079
0080 /*
0081  * CLKID index values
0082  *
0083  * These indices are entirely contrived and do not map onto the hardware.
0084  * It has now been decided to expose everything by default in the DT header:
0085  * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
0086  * to expose, such as the internal muxes and dividers of composite clocks,
0087  * will remain defined here.
0088  */
0089
0090 #define CLKID_MPLL0_DIV     96
0091 #define CLKID_MPLL1_DIV     97
0092 #define CLKID_MPLL2_DIV     98
0093 #define CLKID_CPU_IN_SEL    99
0094 #define CLKID_CPU_IN_DIV2   100
0095 #define CLKID_CPU_IN_DIV3   101
0096 #define CLKID_CPU_SCALE_DIV 102
0097 #define CLKID_CPU_SCALE_OUT_SEL 103
0098 #define CLKID_MPLL_PREDIV   104
0099 #define CLKID_FCLK_DIV2_DIV 105
0100 #define CLKID_FCLK_DIV3_DIV 106
0101 #define CLKID_FCLK_DIV4_DIV 107
0102 #define CLKID_FCLK_DIV5_DIV 108
0103 #define CLKID_FCLK_DIV7_DIV 109
0104 #define CLKID_NAND_SEL      110
0105 #define CLKID_NAND_DIV      111
0106 #define CLKID_PLL_FIXED_DCO 113
0107 #define CLKID_HDMI_PLL_DCO  114
0108 #define CLKID_PLL_SYS_DCO   115
0109 #define CLKID_CPU_CLK_DIV2  116
0110 #define CLKID_CPU_CLK_DIV3  117
0111 #define CLKID_CPU_CLK_DIV4  118
0112 #define CLKID_CPU_CLK_DIV5  119
0113 #define CLKID_CPU_CLK_DIV6  120
0114 #define CLKID_CPU_CLK_DIV7  121
0115 #define CLKID_CPU_CLK_DIV8  122
0116 #define CLKID_APB_SEL       123
0117 #define CLKID_PERIPH_SEL    125
0118 #define CLKID_AXI_SEL       127
0119 #define CLKID_L2_DRAM_SEL   129
0120 #define CLKID_HDMI_PLL_LVDS_OUT 131
0121 #define CLKID_VID_PLL_IN_SEL    133
0122 #define CLKID_VID_PLL_IN_EN 134
0123 #define CLKID_VID_PLL_PRE_DIV   135
0124 #define CLKID_VID_PLL_POST_DIV  136
0125 #define CLKID_VCLK_IN_EN    139
0126 #define CLKID_VCLK_DIV1     140
0127 #define CLKID_VCLK_DIV2_DIV 141
0128 #define CLKID_VCLK_DIV2     142
0129 #define CLKID_VCLK_DIV4_DIV 143
0130 #define CLKID_VCLK_DIV4     144
0131 #define CLKID_VCLK_DIV6_DIV 145
0132 #define CLKID_VCLK_DIV6     146
0133 #define CLKID_VCLK_DIV12_DIV    147
0134 #define CLKID_VCLK_DIV12    148
0135 #define CLKID_VCLK2_IN_EN   150
0136 #define CLKID_VCLK2_DIV1    151
0137 #define CLKID_VCLK2_DIV2_DIV    152
0138 #define CLKID_VCLK2_DIV2    153
0139 #define CLKID_VCLK2_DIV4_DIV    154
0140 #define CLKID_VCLK2_DIV4    155
0141 #define CLKID_VCLK2_DIV6_DIV    156
0142 #define CLKID_VCLK2_DIV6    157
0143 #define CLKID_VCLK2_DIV12_DIV   158
0144 #define CLKID_VCLK2_DIV12   159
0145 #define CLKID_CTS_ENCT_SEL  160
0146 #define CLKID_CTS_ENCP_SEL  162
0147 #define CLKID_CTS_ENCI_SEL  164
0148 #define CLKID_HDMI_TX_PIXEL_SEL 166
0149 #define CLKID_CTS_ENCL_SEL  168
0150 #define CLKID_CTS_VDAC0_SEL 170
0151 #define CLKID_HDMI_SYS_SEL  172
0152 #define CLKID_HDMI_SYS_DIV  173
0153 #define CLKID_MALI_0_SEL    175
0154 #define CLKID_MALI_0_DIV    176
0155 #define CLKID_MALI_0        177
0156 #define CLKID_MALI_1_SEL    178
0157 #define CLKID_MALI_1_DIV    179
0158 #define CLKID_MALI_1        180
0159 #define CLKID_GP_PLL_DCO    181
0160 #define CLKID_GP_PLL        182
0161 #define CLKID_VPU_0_SEL     183
0162 #define CLKID_VPU_0_DIV     184
0163 #define CLKID_VPU_0     185
0164 #define CLKID_VPU_1_SEL     186
0165 #define CLKID_VPU_1_DIV     187
0166 #define CLKID_VPU_1     189
0167 #define CLKID_VDEC_1_SEL    191
0168 #define CLKID_VDEC_1_1_DIV  192
0169 #define CLKID_VDEC_1_1      193
0170 #define CLKID_VDEC_1_2_DIV  194
0171 #define CLKID_VDEC_1_2      195
0172 #define CLKID_VDEC_HCODEC_SEL   197
0173 #define CLKID_VDEC_HCODEC_DIV   198
0174 #define CLKID_VDEC_2_SEL    200
0175 #define CLKID_VDEC_2_DIV    201
0176 #define CLKID_VDEC_HEVC_SEL 203
0177 #define CLKID_VDEC_HEVC_DIV 204
0178 #define CLKID_VDEC_HEVC_EN  205
0179 #define CLKID_CTS_AMCLK_SEL 207
0180 #define CLKID_CTS_AMCLK_DIV 208
0181 #define CLKID_CTS_MCLK_I958_SEL 210
0182 #define CLKID_CTS_MCLK_I958_DIV 211
0183 #define CLKID_VCLK_EN       214
0184 #define CLKID_VCLK2_EN      215
0185 #define CLKID_VID_PLL_LVDS_EN   216
0186 #define CLKID_HDMI_PLL_DCO_IN   217
0187
0188 #define CLK_NR_CLKS     218
0189
0190 /*
0191  * include the CLKID and RESETID that have
0192  * been made part of the stable DT binding
0193  */
0194 #include <dt-bindings/clock/meson8b-clkc.h>
0195 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
0196
0197 #endif /* __MESON8B_H */