clk/meson/meson-aoclk.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Amlogic Meson-AXG Clock Controller Driver
0004  *
0005  * Copyright (c) 2016 BayLibre, SAS.
0006  * Author: Neil Armstrong <narmstrong@baylibre.com>
0007  *
0008  * Copyright (c) 2018 Amlogic, inc.
0009  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
0010  * Author: Yixun Lan <yixun.lan@amlogic.com>
0011  */
0012
0013 #include <linux/platform_device.h>
0014 #include <linux/reset-controller.h>
0015 #include <linux/mfd/syscon.h>
0016 #include <linux/of_device.h>
0017 #include <linux/module.h>
0018
0019 #include <linux/slab.h>
0020 #include "meson-aoclk.h"
0021
0022 static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
0023                    unsigned long id)
0024 {
0025     struct meson_aoclk_reset_controller *rstc =
0026         container_of(rcdev, struct meson_aoclk_reset_controller, reset);
0027
0028     return regmap_write(rstc->regmap, rstc->data->reset_reg,
0029                 BIT(rstc->data->reset[id]));
0030 }
0031
0032 static const struct reset_control_ops meson_aoclk_reset_ops = {
0033     .reset = meson_aoclk_do_reset,
0034 };
0035
0036 int meson_aoclkc_probe(struct platform_device *pdev)
0037 {
0038     struct meson_aoclk_reset_controller *rstc;
0039     struct meson_aoclk_data *data;
0040     struct device *dev = &pdev->dev;
0041     struct regmap *regmap;
0042     int ret, clkid;
0043
0044     data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
0045     if (!data)
0046         return -ENODEV;
0047
0048     rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
0049     if (!rstc)
0050         return -ENOMEM;
0051
0052     regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
0053     if (IS_ERR(regmap)) {
0054         dev_err(dev, "failed to get regmap\n");
0055         return PTR_ERR(regmap);
0056     }
0057
0058     /* Reset Controller */
0059     rstc->data = data;
0060     rstc->regmap = regmap;
0061     rstc->reset.ops = &meson_aoclk_reset_ops;
0062     rstc->reset.nr_resets = data->num_reset;
0063     rstc->reset.of_node = dev->of_node;
0064     ret = devm_reset_controller_register(dev, &rstc->reset);
0065     if (ret) {
0066         dev_err(dev, "failed to register reset controller\n");
0067         return ret;
0068     }
0069
0070     /* Populate regmap */
0071     for (clkid = 0; clkid < data->num_clks; clkid++)
0072         data->clks[clkid]->map = regmap;
0073
0074     /* Register all clks */
0075     for (clkid = 0; clkid < data->hw_data->num; clkid++) {
0076         if (!data->hw_data->hws[clkid])
0077             continue;
0078
0079         ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
0080         if (ret) {
0081             dev_err(dev, "Clock registration failed\n");
0082             return ret;
0083         }
0084     }
0085
0086     return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
0087         (void *) data->hw_data);
0088 }
0089 EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
0090 MODULE_LICENSE("GPL v2");