clk/meson/gxbb-aoclk.c

0001 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
0002 /*
0003  * Copyright (c) 2016 BayLibre, SAS.
0004  * Author: Neil Armstrong <narmstrong@baylibre.com>
0005  */
0006 #include <linux/platform_device.h>
0007 #include <linux/mfd/syscon.h>
0008 #include <linux/module.h>
0009 #include "meson-aoclk.h"
0010 #include "gxbb-aoclk.h"
0011
0012 #include "clk-regmap.h"
0013 #include "clk-dualdiv.h"
0014
0015 /* AO Configuration Clock registers offsets */
0016 #define AO_RTI_PWR_CNTL_REG1    0x0c
0017 #define AO_RTI_PWR_CNTL_REG0    0x10
0018 #define AO_RTI_GEN_CNTL_REG0    0x40
0019 #define AO_OSCIN_CNTL       0x58
0020 #define AO_CRT_CLK_CNTL1    0x68
0021 #define AO_RTC_ALT_CLK_CNTL0    0x94
0022 #define AO_RTC_ALT_CLK_CNTL1    0x98
0023
0024 #define GXBB_AO_GATE(_name, _bit)                   \
0025 static struct clk_regmap _name##_ao = {                 \
0026     .data = &(struct clk_regmap_gate_data) {            \
0027         .offset = AO_RTI_GEN_CNTL_REG0,             \
0028         .bit_idx = (_bit),                  \
0029     },                              \
0030     .hw.init = &(struct clk_init_data) {                \
0031         .name = #_name "_ao",                   \
0032         .ops = &clk_regmap_gate_ops,                \
0033         .parent_data = &(const struct clk_parent_data) {    \
0034             .fw_name = "mpeg-clk",              \
0035         },                          \
0036         .num_parents = 1,                   \
0037         .flags = CLK_IGNORE_UNUSED,             \
0038     },                              \
0039 }
0040
0041 GXBB_AO_GATE(remote, 0);
0042 GXBB_AO_GATE(i2c_master, 1);
0043 GXBB_AO_GATE(i2c_slave, 2);
0044 GXBB_AO_GATE(uart1, 3);
0045 GXBB_AO_GATE(uart2, 5);
0046 GXBB_AO_GATE(ir_blaster, 6);
0047
0048 static struct clk_regmap ao_cts_oscin = {
0049     .data = &(struct clk_regmap_gate_data){
0050         .offset = AO_RTI_PWR_CNTL_REG0,
0051         .bit_idx = 6,
0052     },
0053     .hw.init = &(struct clk_init_data){
0054         .name = "ao_cts_oscin",
0055         .ops = &clk_regmap_gate_ro_ops,
0056         .parent_data = &(const struct clk_parent_data) {
0057             .fw_name = "xtal",
0058         },
0059         .num_parents = 1,
0060     },
0061 };
0062
0063 static struct clk_regmap ao_32k_pre = {
0064     .data = &(struct clk_regmap_gate_data){
0065         .offset = AO_RTC_ALT_CLK_CNTL0,
0066         .bit_idx = 31,
0067     },
0068     .hw.init = &(struct clk_init_data){
0069         .name = "ao_32k_pre",
0070         .ops = &clk_regmap_gate_ops,
0071         .parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
0072         .num_parents = 1,
0073     },
0074 };
0075
0076 static const struct meson_clk_dualdiv_param gxbb_32k_div_table[] = {
0077     {
0078         .dual   = 1,
0079         .n1 = 733,
0080         .m1 = 8,
0081         .n2 = 732,
0082         .m2 = 11,
0083     }, {}
0084 };
0085
0086 static struct clk_regmap ao_32k_div = {
0087     .data = &(struct meson_clk_dualdiv_data){
0088         .n1 = {
0089             .reg_off = AO_RTC_ALT_CLK_CNTL0,
0090             .shift   = 0,
0091             .width   = 12,
0092         },
0093         .n2 = {
0094             .reg_off = AO_RTC_ALT_CLK_CNTL0,
0095             .shift   = 12,
0096             .width   = 12,
0097         },
0098         .m1 = {
0099             .reg_off = AO_RTC_ALT_CLK_CNTL1,
0100             .shift   = 0,
0101             .width   = 12,
0102         },
0103         .m2 = {
0104             .reg_off = AO_RTC_ALT_CLK_CNTL1,
0105             .shift   = 12,
0106             .width   = 12,
0107         },
0108         .dual = {
0109             .reg_off = AO_RTC_ALT_CLK_CNTL0,
0110             .shift   = 28,
0111             .width   = 1,
0112         },
0113         .table = gxbb_32k_div_table,
0114     },
0115     .hw.init = &(struct clk_init_data){
0116         .name = "ao_32k_div",
0117         .ops = &meson_clk_dualdiv_ops,
0118         .parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
0119         .num_parents = 1,
0120     },
0121 };
0122
0123 static struct clk_regmap ao_32k_sel = {
0124     .data = &(struct clk_regmap_mux_data) {
0125         .offset = AO_RTC_ALT_CLK_CNTL1,
0126         .mask = 0x1,
0127         .shift = 24,
0128         .flags = CLK_MUX_ROUND_CLOSEST,
0129     },
0130     .hw.init = &(struct clk_init_data){
0131         .name = "ao_32k_sel",
0132         .ops = &clk_regmap_mux_ops,
0133         .parent_hws = (const struct clk_hw *[]) {
0134             &ao_32k_div.hw,
0135             &ao_32k_pre.hw
0136         },
0137         .num_parents = 2,
0138         .flags = CLK_SET_RATE_PARENT,
0139     },
0140 };
0141
0142 static struct clk_regmap ao_32k = {
0143     .data = &(struct clk_regmap_gate_data){
0144         .offset = AO_RTC_ALT_CLK_CNTL0,
0145         .bit_idx = 30,
0146     },
0147     .hw.init = &(struct clk_init_data){
0148         .name = "ao_32k",
0149         .ops = &clk_regmap_gate_ops,
0150         .parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
0151         .num_parents = 1,
0152         .flags = CLK_SET_RATE_PARENT,
0153     },
0154 };
0155
0156 static struct clk_regmap ao_cts_rtc_oscin = {
0157     .data = &(struct clk_regmap_mux_data) {
0158         .offset = AO_RTI_PWR_CNTL_REG0,
0159         .mask = 0x7,
0160         .shift = 10,
0161         .table = (u32[]){ 1, 2, 3, 4 },
0162         .flags = CLK_MUX_ROUND_CLOSEST,
0163     },
0164     .hw.init = &(struct clk_init_data){
0165         .name = "ao_cts_rtc_oscin",
0166         .ops = &clk_regmap_mux_ops,
0167         .parent_data = (const struct clk_parent_data []) {
0168             { .fw_name = "ext-32k-0", },
0169             { .fw_name = "ext-32k-1", },
0170             { .fw_name = "ext-32k-2", },
0171             { .hw = &ao_32k.hw },
0172         },
0173         .num_parents = 4,
0174         .flags = CLK_SET_RATE_PARENT,
0175     },
0176 };
0177
0178 static struct clk_regmap ao_clk81 = {
0179     .data = &(struct clk_regmap_mux_data) {
0180         .offset = AO_RTI_PWR_CNTL_REG0,
0181         .mask = 0x1,
0182         .shift = 0,
0183         .flags = CLK_MUX_ROUND_CLOSEST,
0184     },
0185     .hw.init = &(struct clk_init_data){
0186         .name = "ao_clk81",
0187         .ops = &clk_regmap_mux_ro_ops,
0188         .parent_data = (const struct clk_parent_data []) {
0189             { .fw_name = "mpeg-clk", },
0190             { .hw = &ao_cts_rtc_oscin.hw },
0191         },
0192         .num_parents = 2,
0193         .flags = CLK_SET_RATE_PARENT,
0194     },
0195 };
0196
0197 static struct clk_regmap ao_cts_cec = {
0198     .data = &(struct clk_regmap_mux_data) {
0199         .offset = AO_CRT_CLK_CNTL1,
0200         .mask = 0x1,
0201         .shift = 27,
0202         .flags = CLK_MUX_ROUND_CLOSEST,
0203     },
0204     .hw.init = &(struct clk_init_data){
0205         .name = "ao_cts_cec",
0206         .ops = &clk_regmap_mux_ops,
0207         /*
0208          * FIXME: The 'fixme' parent obviously does not exist.
0209          *
0210          * ATM, CCF won't call get_parent() if num_parents is 1. It
0211          * does not allow NULL as a parent name either.
0212          *
0213          * On this particular mux, we only know the input #1 parent
0214          * but, on boot, unknown input #0 is set, so it is critical
0215          * to call .get_parent() on it
0216          *
0217          * Until CCF gets fixed, adding this fake parent that won't
0218          * ever be registered should work around the problem
0219          */
0220         .parent_data = (const struct clk_parent_data []) {
0221             { .name = "fixme", .index = -1, },
0222             { .hw = &ao_cts_rtc_oscin.hw },
0223         },
0224         .num_parents = 2,
0225         .flags = CLK_SET_RATE_PARENT,
0226     },
0227 };
0228
0229 static const unsigned int gxbb_aoclk_reset[] = {
0230     [RESET_AO_REMOTE] = 16,
0231     [RESET_AO_I2C_MASTER] = 18,
0232     [RESET_AO_I2C_SLAVE] = 19,
0233     [RESET_AO_UART1] = 17,
0234     [RESET_AO_UART2] = 22,
0235     [RESET_AO_IR_BLASTER] = 23,
0236 };
0237
0238 static struct clk_regmap *gxbb_aoclk[] = {
0239     &remote_ao,
0240     &i2c_master_ao,
0241     &i2c_slave_ao,
0242     &uart1_ao,
0243     &uart2_ao,
0244     &ir_blaster_ao,
0245     &ao_cts_oscin,
0246     &ao_32k_pre,
0247     &ao_32k_div,
0248     &ao_32k_sel,
0249     &ao_32k,
0250     &ao_cts_rtc_oscin,
0251     &ao_clk81,
0252     &ao_cts_cec,
0253 };
0254
0255 static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
0256     .hws = {
0257         [CLKID_AO_REMOTE] = &remote_ao.hw,
0258         [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
0259         [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
0260         [CLKID_AO_UART1] = &uart1_ao.hw,
0261         [CLKID_AO_UART2] = &uart2_ao.hw,
0262         [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
0263         [CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
0264         [CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
0265         [CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
0266         [CLKID_AO_32K_DIV] = &ao_32k_div.hw,
0267         [CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
0268         [CLKID_AO_32K] = &ao_32k.hw,
0269         [CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
0270         [CLKID_AO_CLK81] = &ao_clk81.hw,
0271     },
0272     .num = NR_CLKS,
0273 };
0274
0275 static const struct meson_aoclk_data gxbb_aoclkc_data = {
0276     .reset_reg  = AO_RTI_GEN_CNTL_REG0,
0277     .num_reset  = ARRAY_SIZE(gxbb_aoclk_reset),
0278     .reset      = gxbb_aoclk_reset,
0279     .num_clks   = ARRAY_SIZE(gxbb_aoclk),
0280     .clks       = gxbb_aoclk,
0281     .hw_data    = &gxbb_aoclk_onecell_data,
0282 };
0283
0284 static const struct of_device_id gxbb_aoclkc_match_table[] = {
0285     {
0286         .compatible = "amlogic,meson-gx-aoclkc",
0287         .data       = &gxbb_aoclkc_data,
0288     },
0289     { }
0290 };
0291 MODULE_DEVICE_TABLE(of, gxbb_aoclkc_match_table);
0292
0293 static struct platform_driver gxbb_aoclkc_driver = {
0294     .probe      = meson_aoclkc_probe,
0295     .driver     = {
0296         .name   = "gxbb-aoclkc",
0297         .of_match_table = gxbb_aoclkc_match_table,
0298     },
0299 };
0300 module_platform_driver(gxbb_aoclkc_driver);
0301 MODULE_LICENSE("GPL v2");