clk/meson/clk-mpll.c

0001 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
0002 /*
0003  * Copyright (c) 2016 AmLogic, Inc.
0004  * Author: Michael Turquette <mturquette@baylibre.com>
0005  */
0006
0007 /*
0008  * MultiPhase Locked Loops are outputs from a PLL with additional frequency
0009  * scaling capabilities. MPLL rates are calculated as:
0010  *
0011  * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
0012  */
0013
0014 #include <linux/clk-provider.h>
0015 #include <linux/module.h>
0016 #include <linux/spinlock.h>
0017
0018 #include "clk-regmap.h"
0019 #include "clk-mpll.h"
0020
0021 #define SDM_DEN 16384
0022 #define N2_MIN  4
0023 #define N2_MAX  511
0024
0025 static inline struct meson_clk_mpll_data *
0026 meson_clk_mpll_data(struct clk_regmap *clk)
0027 {
0028     return (struct meson_clk_mpll_data *)clk->data;
0029 }
0030
0031 static long rate_from_params(unsigned long parent_rate,
0032                  unsigned int sdm,
0033                  unsigned int n2)
0034 {
0035     unsigned long divisor = (SDM_DEN * n2) + sdm;
0036
0037     if (n2 < N2_MIN)
0038         return -EINVAL;
0039
0040     return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
0041 }
0042
0043 static void params_from_rate(unsigned long requested_rate,
0044                  unsigned long parent_rate,
0045                  unsigned int *sdm,
0046                  unsigned int *n2,
0047                  u8 flags)
0048 {
0049     uint64_t div = parent_rate;
0050     uint64_t frac = do_div(div, requested_rate);
0051
0052     frac *= SDM_DEN;
0053
0054     if (flags & CLK_MESON_MPLL_ROUND_CLOSEST)
0055         *sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate);
0056     else
0057         *sdm = DIV_ROUND_UP_ULL(frac, requested_rate);
0058
0059     if (*sdm == SDM_DEN) {
0060         *sdm = 0;
0061         div += 1;
0062     }
0063
0064     if (div < N2_MIN) {
0065         *n2 = N2_MIN;
0066         *sdm = 0;
0067     } else if (div > N2_MAX) {
0068         *n2 = N2_MAX;
0069         *sdm = SDM_DEN - 1;
0070     } else {
0071         *n2 = div;
0072     }
0073 }
0074
0075 static unsigned long mpll_recalc_rate(struct clk_hw *hw,
0076         unsigned long parent_rate)
0077 {
0078     struct clk_regmap *clk = to_clk_regmap(hw);
0079     struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
0080     unsigned int sdm, n2;
0081     long rate;
0082
0083     sdm = meson_parm_read(clk->map, &mpll->sdm);
0084     n2 = meson_parm_read(clk->map, &mpll->n2);
0085
0086     rate = rate_from_params(parent_rate, sdm, n2);
0087     return rate < 0 ? 0 : rate;
0088 }
0089
0090 static long mpll_round_rate(struct clk_hw *hw,
0091                 unsigned long rate,
0092                 unsigned long *parent_rate)
0093 {
0094     struct clk_regmap *clk = to_clk_regmap(hw);
0095     struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
0096     unsigned int sdm, n2;
0097
0098     params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);
0099     return rate_from_params(*parent_rate, sdm, n2);
0100 }
0101
0102 static int mpll_set_rate(struct clk_hw *hw,
0103              unsigned long rate,
0104              unsigned long parent_rate)
0105 {
0106     struct clk_regmap *clk = to_clk_regmap(hw);
0107     struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
0108     unsigned int sdm, n2;
0109     unsigned long flags = 0;
0110
0111     params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
0112
0113     if (mpll->lock)
0114         spin_lock_irqsave(mpll->lock, flags);
0115     else
0116         __acquire(mpll->lock);
0117
0118     /* Set the fractional part */
0119     meson_parm_write(clk->map, &mpll->sdm, sdm);
0120
0121     /* Set the integer divider part */
0122     meson_parm_write(clk->map, &mpll->n2, n2);
0123
0124     if (mpll->lock)
0125         spin_unlock_irqrestore(mpll->lock, flags);
0126     else
0127         __release(mpll->lock);
0128
0129     return 0;
0130 }
0131
0132 static int mpll_init(struct clk_hw *hw)
0133 {
0134     struct clk_regmap *clk = to_clk_regmap(hw);
0135     struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
0136
0137     if (mpll->init_count)
0138         regmap_multi_reg_write(clk->map, mpll->init_regs,
0139                        mpll->init_count);
0140
0141     /* Enable the fractional part */
0142     meson_parm_write(clk->map, &mpll->sdm_en, 1);
0143
0144     /* Set spread spectrum if possible */
0145     if (MESON_PARM_APPLICABLE(&mpll->ssen)) {
0146         unsigned int ss =
0147             mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;
0148         meson_parm_write(clk->map, &mpll->ssen, ss);
0149     }
0150
0151     /* Set the magic misc bit if required */
0152     if (MESON_PARM_APPLICABLE(&mpll->misc))
0153         meson_parm_write(clk->map, &mpll->misc, 1);
0154
0155     return 0;
0156 }
0157
0158 const struct clk_ops meson_clk_mpll_ro_ops = {
0159     .recalc_rate    = mpll_recalc_rate,
0160     .round_rate = mpll_round_rate,
0161 };
0162 EXPORT_SYMBOL_GPL(meson_clk_mpll_ro_ops);
0163
0164 const struct clk_ops meson_clk_mpll_ops = {
0165     .recalc_rate    = mpll_recalc_rate,
0166     .round_rate = mpll_round_rate,
0167     .set_rate   = mpll_set_rate,
0168     .init       = mpll_init,
0169 };
0170 EXPORT_SYMBOL_GPL(meson_clk_mpll_ops);
0171
0172 MODULE_DESCRIPTION("Amlogic MPLL driver");
0173 MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>");
0174 MODULE_LICENSE("GPL v2");