clk/meson/axg-audio.c

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003  * Copyright (c) 2018 BayLibre, SAS.
0004  * Author: Jerome Brunet <jbrunet@baylibre.com>
0005  */
0006
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/init.h>
0010 #include <linux/of_device.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014 #include <linux/reset.h>
0015 #include <linux/reset-controller.h>
0016 #include <linux/slab.h>
0017
0018 #include "axg-audio.h"
0019 #include "clk-regmap.h"
0020 #include "clk-phase.h"
0021 #include "sclk-div.h"
0022
0023 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {          \
0024     .data = &(struct clk_regmap_gate_data){             \
0025         .offset = (_reg),                   \
0026         .bit_idx = (_bit),                  \
0027     },                              \
0028     .hw.init = &(struct clk_init_data) {                \
0029         .name = "aud_"#_name,                   \
0030         .ops = &clk_regmap_gate_ops,                \
0031         .parent_names = (const char *[]){ #_pname },        \
0032         .num_parents = 1,                   \
0033         .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),     \
0034     },                              \
0035 }
0036
0037 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \
0038     .data = &(struct clk_regmap_mux_data){              \
0039         .offset = (_reg),                   \
0040         .mask = (_mask),                    \
0041         .shift = (_shift),                  \
0042         .flags = (_dflags),                 \
0043     },                              \
0044     .hw.init = &(struct clk_init_data){             \
0045         .name = "aud_"#_name,                   \
0046         .ops = &clk_regmap_mux_ops,             \
0047         .parent_data = _pdata,                  \
0048         .num_parents = ARRAY_SIZE(_pdata),          \
0049         .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),     \
0050     },                              \
0051 }
0052
0053 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
0054     .data = &(struct clk_regmap_div_data){              \
0055         .offset = (_reg),                   \
0056         .shift = (_shift),                  \
0057         .width = (_width),                  \
0058         .flags = (_dflags),                 \
0059     },                              \
0060     .hw.init = &(struct clk_init_data){             \
0061         .name = "aud_"#_name,                   \
0062         .ops = &clk_regmap_divider_ops,             \
0063         .parent_names = (const char *[]){ #_pname },        \
0064         .num_parents = 1,                   \
0065         .flags = (_iflags),                 \
0066     },                              \
0067 }
0068
0069 #define AUD_PCLK_GATE(_name, _reg, _bit) {              \
0070     .data = &(struct clk_regmap_gate_data){             \
0071         .offset = (_reg),                   \
0072         .bit_idx = (_bit),                  \
0073     },                              \
0074     .hw.init = &(struct clk_init_data) {                \
0075         .name = "aud_"#_name,                   \
0076         .ops = &clk_regmap_gate_ops,                \
0077         .parent_names = (const char *[]){ "aud_top" },      \
0078         .num_parents = 1,                   \
0079     },                              \
0080 }
0081
0082 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,       \
0083              _hi_shift, _hi_width, _pname, _iflags) {       \
0084     .data = &(struct meson_sclk_div_data) {             \
0085         .div = {                        \
0086             .reg_off = (_reg),              \
0087             .shift   = (_div_shift),            \
0088             .width   = (_div_width),            \
0089         },                          \
0090         .hi = {                         \
0091             .reg_off = (_reg),              \
0092             .shift   = (_hi_shift),             \
0093             .width   = (_hi_width),             \
0094         },                          \
0095     },                              \
0096     .hw.init = &(struct clk_init_data) {                \
0097         .name = "aud_"#_name,                   \
0098         .ops = &meson_sclk_div_ops,             \
0099         .parent_names = (const char *[]){ #_pname },        \
0100         .num_parents = 1,                   \
0101         .flags = (_iflags),                 \
0102     },                              \
0103 }
0104
0105 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,    \
0106              _pname, _iflags) {                 \
0107     .data = &(struct meson_clk_triphase_data) {         \
0108         .ph0 = {                        \
0109             .reg_off = (_reg),              \
0110             .shift   = (_shift0),               \
0111             .width   = (_width),                \
0112         },                          \
0113         .ph1 = {                        \
0114             .reg_off = (_reg),              \
0115             .shift   = (_shift1),               \
0116             .width   = (_width),                \
0117         },                          \
0118         .ph2 = {                        \
0119             .reg_off = (_reg),              \
0120             .shift   = (_shift2),               \
0121             .width   = (_width),                \
0122         },                          \
0123     },                              \
0124     .hw.init = &(struct clk_init_data) {                \
0125         .name = "aud_"#_name,                   \
0126         .ops = &meson_clk_triphase_ops,             \
0127         .parent_names = (const char *[]){ #_pname },        \
0128         .num_parents = 1,                   \
0129         .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),     \
0130     },                              \
0131 }
0132
0133 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) {   \
0134     .data = &(struct meson_clk_phase_data) {            \
0135         .ph = {                         \
0136             .reg_off = (_reg),              \
0137             .shift   = (_shift),                \
0138             .width   = (_width),                \
0139         },                          \
0140     },                              \
0141     .hw.init = &(struct clk_init_data) {                \
0142         .name = "aud_"#_name,                   \
0143         .ops = &meson_clk_phase_ops,                \
0144         .parent_names = (const char *[]){ #_pname },        \
0145         .num_parents = 1,                   \
0146         .flags = (_iflags),                 \
0147     },                              \
0148 }
0149
0150 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname,  \
0151             _iflags) {                      \
0152     .data = &(struct meson_sclk_ws_inv_data) {          \
0153         .ph = {                         \
0154             .reg_off = (_reg),              \
0155             .shift   = (_shift_ph),             \
0156             .width   = (_width),                \
0157         },                          \
0158         .ws = {                         \
0159             .reg_off = (_reg),              \
0160             .shift   = (_shift_ws),             \
0161             .width   = (_width),                \
0162         },                          \
0163     },                              \
0164     .hw.init = &(struct clk_init_data) {                \
0165         .name = "aud_"#_name,                   \
0166         .ops = &meson_clk_phase_ops,                \
0167         .parent_names = (const char *[]){ #_pname },        \
0168         .num_parents = 1,                   \
0169         .flags = (_iflags),                 \
0170     },                              \
0171 }
0172
0173 /* Audio Master Clocks */
0174 static const struct clk_parent_data mst_mux_parent_data[] = {
0175     { .fw_name = "mst_in0", },
0176     { .fw_name = "mst_in1", },
0177     { .fw_name = "mst_in2", },
0178     { .fw_name = "mst_in3", },
0179     { .fw_name = "mst_in4", },
0180     { .fw_name = "mst_in5", },
0181     { .fw_name = "mst_in6", },
0182     { .fw_name = "mst_in7", },
0183 };
0184
0185 #define AUD_MST_MUX(_name, _reg, _flag)                 \
0186     AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,          \
0187         mst_mux_parent_data, 0)
0188 #define AUD_MST_DIV(_name, _reg, _flag)                 \
0189     AUD_DIV(_name##_div, _reg, 0, 16, _flag,            \
0190         aud_##_name##_sel, CLK_SET_RATE_PARENT)
0191 #define AUD_MST_MCLK_GATE(_name, _reg)                  \
0192     AUD_GATE(_name, _reg, 31, aud_##_name##_div,            \
0193          CLK_SET_RATE_PARENT)
0194
0195 #define AUD_MST_MCLK_MUX(_name, _reg)                   \
0196     AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
0197 #define AUD_MST_MCLK_DIV(_name, _reg)                   \
0198     AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
0199
0200 #define AUD_MST_SYS_MUX(_name, _reg)                    \
0201     AUD_MST_MUX(_name, _reg, 0)
0202 #define AUD_MST_SYS_DIV(_name, _reg)                    \
0203     AUD_MST_DIV(_name, _reg, 0)
0204
0205 /* Sample Clocks */
0206 #define AUD_MST_SCLK_PRE_EN(_name, _reg)                \
0207     AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,           \
0208          aud_mst_##_name##_mclk, 0)
0209 #define AUD_MST_SCLK_DIV(_name, _reg)                   \
0210     AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,    \
0211              aud_mst_##_name##_sclk_pre_en,         \
0212              CLK_SET_RATE_PARENT)
0213 #define AUD_MST_SCLK_POST_EN(_name, _reg)               \
0214     AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,          \
0215          aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
0216 #define AUD_MST_SCLK(_name, _reg)                   \
0217     AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,      \
0218              aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
0219
0220 #define AUD_MST_LRCLK_DIV(_name, _reg)                  \
0221     AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,  \
0222              aud_mst_##_name##_sclk_post_en, 0)
0223 #define AUD_MST_LRCLK(_name, _reg)                  \
0224     AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,     \
0225              aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
0226
0227 /* TDM bit clock sources */
0228 static const struct clk_parent_data tdm_sclk_parent_data[] = {
0229     { .name = "aud_mst_a_sclk", .index = -1, },
0230     { .name = "aud_mst_b_sclk", .index = -1, },
0231     { .name = "aud_mst_c_sclk", .index = -1, },
0232     { .name = "aud_mst_d_sclk", .index = -1, },
0233     { .name = "aud_mst_e_sclk", .index = -1, },
0234     { .name = "aud_mst_f_sclk", .index = -1, },
0235     { .fw_name = "slv_sclk0", },
0236     { .fw_name = "slv_sclk1", },
0237     { .fw_name = "slv_sclk2", },
0238     { .fw_name = "slv_sclk3", },
0239     { .fw_name = "slv_sclk4", },
0240     { .fw_name = "slv_sclk5", },
0241     { .fw_name = "slv_sclk6", },
0242     { .fw_name = "slv_sclk7", },
0243     { .fw_name = "slv_sclk8", },
0244     { .fw_name = "slv_sclk9", },
0245 };
0246
0247 /* TDM sample clock sources */
0248 static const struct clk_parent_data tdm_lrclk_parent_data[] = {
0249     { .name = "aud_mst_a_lrclk", .index = -1, },
0250     { .name = "aud_mst_b_lrclk", .index = -1, },
0251     { .name = "aud_mst_c_lrclk", .index = -1, },
0252     { .name = "aud_mst_d_lrclk", .index = -1, },
0253     { .name = "aud_mst_e_lrclk", .index = -1, },
0254     { .name = "aud_mst_f_lrclk", .index = -1, },
0255     { .fw_name = "slv_lrclk0", },
0256     { .fw_name = "slv_lrclk1", },
0257     { .fw_name = "slv_lrclk2", },
0258     { .fw_name = "slv_lrclk3", },
0259     { .fw_name = "slv_lrclk4", },
0260     { .fw_name = "slv_lrclk5", },
0261     { .fw_name = "slv_lrclk6", },
0262     { .fw_name = "slv_lrclk7", },
0263     { .fw_name = "slv_lrclk8", },
0264     { .fw_name = "slv_lrclk9", },
0265 };
0266
0267 #define AUD_TDM_SCLK_MUX(_name, _reg)                   \
0268     AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,           \
0269         CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
0270 #define AUD_TDM_SCLK_PRE_EN(_name, _reg)                \
0271     AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,            \
0272          aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
0273 #define AUD_TDM_SCLK_POST_EN(_name, _reg)               \
0274     AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,           \
0275          aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
0276 #define AUD_TDM_SCLK(_name, _reg)                   \
0277     AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29,           \
0278           aud_tdm##_name##_sclk_post_en,            \
0279           CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
0280 #define AUD_TDM_SCLK_WS(_name, _reg)                    \
0281     AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28,         \
0282             aud_tdm##_name##_sclk_post_en,          \
0283             CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
0284
0285 #define AUD_TDM_LRLCK(_name, _reg)                  \
0286     AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,          \
0287         CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
0288
0289 /* Pad master clock sources */
0290 static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
0291     { .name = "aud_mst_a_mclk", .index = -1,  },
0292     { .name = "aud_mst_b_mclk", .index = -1,  },
0293     { .name = "aud_mst_c_mclk", .index = -1,  },
0294     { .name = "aud_mst_d_mclk", .index = -1,  },
0295     { .name = "aud_mst_e_mclk", .index = -1,  },
0296     { .name = "aud_mst_f_mclk", .index = -1,  },
0297 };
0298
0299 /* Pad bit clock sources */
0300 static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
0301     { .name = "aud_mst_a_sclk", .index = -1, },
0302     { .name = "aud_mst_b_sclk", .index = -1, },
0303     { .name = "aud_mst_c_sclk", .index = -1, },
0304     { .name = "aud_mst_d_sclk", .index = -1, },
0305     { .name = "aud_mst_e_sclk", .index = -1, },
0306     { .name = "aud_mst_f_sclk", .index = -1, },
0307 };
0308
0309 /* Pad sample clock sources */
0310 static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
0311     { .name = "aud_mst_a_lrclk", .index = -1, },
0312     { .name = "aud_mst_b_lrclk", .index = -1, },
0313     { .name = "aud_mst_c_lrclk", .index = -1, },
0314     { .name = "aud_mst_d_lrclk", .index = -1, },
0315     { .name = "aud_mst_e_lrclk", .index = -1, },
0316     { .name = "aud_mst_f_lrclk", .index = -1, },
0317 };
0318
0319 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)     \
0320     AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents,      \
0321         CLK_SET_RATE_NO_REPARENT)
0322
0323 /* Common Clocks */
0324 static struct clk_regmap ddr_arb =
0325     AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
0326 static struct clk_regmap pdm =
0327     AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
0328 static struct clk_regmap tdmin_a =
0329     AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
0330 static struct clk_regmap tdmin_b =
0331     AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
0332 static struct clk_regmap tdmin_c =
0333     AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
0334 static struct clk_regmap tdmin_lb =
0335     AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
0336 static struct clk_regmap tdmout_a =
0337     AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
0338 static struct clk_regmap tdmout_b =
0339     AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
0340 static struct clk_regmap tdmout_c =
0341     AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
0342 static struct clk_regmap frddr_a =
0343     AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
0344 static struct clk_regmap frddr_b =
0345     AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
0346 static struct clk_regmap frddr_c =
0347     AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
0348 static struct clk_regmap toddr_a =
0349     AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
0350 static struct clk_regmap toddr_b =
0351     AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
0352 static struct clk_regmap toddr_c =
0353     AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
0354 static struct clk_regmap loopback =
0355     AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
0356 static struct clk_regmap spdifin =
0357     AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
0358 static struct clk_regmap spdifout =
0359     AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
0360 static struct clk_regmap resample =
0361     AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
0362 static struct clk_regmap power_detect =
0363     AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
0364
0365 static struct clk_regmap spdifout_clk_sel =
0366     AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
0367 static struct clk_regmap pdm_dclk_sel =
0368     AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
0369 static struct clk_regmap spdifin_clk_sel =
0370     AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
0371 static struct clk_regmap pdm_sysclk_sel =
0372     AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
0373 static struct clk_regmap spdifout_b_clk_sel =
0374     AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
0375
0376 static struct clk_regmap spdifout_clk_div =
0377     AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
0378 static struct clk_regmap pdm_dclk_div =
0379     AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
0380 static struct clk_regmap spdifin_clk_div =
0381     AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
0382 static struct clk_regmap pdm_sysclk_div =
0383     AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
0384 static struct clk_regmap spdifout_b_clk_div =
0385     AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
0386
0387 static struct clk_regmap spdifout_clk =
0388     AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
0389 static struct clk_regmap spdifin_clk =
0390     AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
0391 static struct clk_regmap pdm_dclk =
0392     AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
0393 static struct clk_regmap pdm_sysclk =
0394     AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
0395 static struct clk_regmap spdifout_b_clk =
0396     AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
0397
0398 static struct clk_regmap mst_a_sclk_pre_en =
0399     AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
0400 static struct clk_regmap mst_b_sclk_pre_en =
0401     AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
0402 static struct clk_regmap mst_c_sclk_pre_en =
0403     AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
0404 static struct clk_regmap mst_d_sclk_pre_en =
0405     AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
0406 static struct clk_regmap mst_e_sclk_pre_en =
0407     AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
0408 static struct clk_regmap mst_f_sclk_pre_en =
0409     AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
0410
0411 static struct clk_regmap mst_a_sclk_div =
0412     AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
0413 static struct clk_regmap mst_b_sclk_div =
0414     AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
0415 static struct clk_regmap mst_c_sclk_div =
0416     AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
0417 static struct clk_regmap mst_d_sclk_div =
0418     AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
0419 static struct clk_regmap mst_e_sclk_div =
0420     AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
0421 static struct clk_regmap mst_f_sclk_div =
0422     AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
0423
0424 static struct clk_regmap mst_a_sclk_post_en =
0425     AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
0426 static struct clk_regmap mst_b_sclk_post_en =
0427     AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
0428 static struct clk_regmap mst_c_sclk_post_en =
0429     AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
0430 static struct clk_regmap mst_d_sclk_post_en =
0431     AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
0432 static struct clk_regmap mst_e_sclk_post_en =
0433     AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
0434 static struct clk_regmap mst_f_sclk_post_en =
0435     AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
0436
0437 static struct clk_regmap mst_a_sclk =
0438     AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
0439 static struct clk_regmap mst_b_sclk =
0440     AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
0441 static struct clk_regmap mst_c_sclk =
0442     AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
0443 static struct clk_regmap mst_d_sclk =
0444     AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
0445 static struct clk_regmap mst_e_sclk =
0446     AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
0447 static struct clk_regmap mst_f_sclk =
0448     AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
0449
0450 static struct clk_regmap mst_a_lrclk_div =
0451     AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
0452 static struct clk_regmap mst_b_lrclk_div =
0453     AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
0454 static struct clk_regmap mst_c_lrclk_div =
0455     AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
0456 static struct clk_regmap mst_d_lrclk_div =
0457     AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
0458 static struct clk_regmap mst_e_lrclk_div =
0459     AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
0460 static struct clk_regmap mst_f_lrclk_div =
0461     AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
0462
0463 static struct clk_regmap mst_a_lrclk =
0464     AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
0465 static struct clk_regmap mst_b_lrclk =
0466     AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
0467 static struct clk_regmap mst_c_lrclk =
0468     AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
0469 static struct clk_regmap mst_d_lrclk =
0470     AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
0471 static struct clk_regmap mst_e_lrclk =
0472     AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
0473 static struct clk_regmap mst_f_lrclk =
0474     AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
0475
0476 static struct clk_regmap tdmin_a_sclk_sel =
0477     AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
0478 static struct clk_regmap tdmin_b_sclk_sel =
0479     AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
0480 static struct clk_regmap tdmin_c_sclk_sel =
0481     AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
0482 static struct clk_regmap tdmin_lb_sclk_sel =
0483     AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
0484 static struct clk_regmap tdmout_a_sclk_sel =
0485     AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
0486 static struct clk_regmap tdmout_b_sclk_sel =
0487     AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
0488 static struct clk_regmap tdmout_c_sclk_sel =
0489     AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
0490
0491 static struct clk_regmap tdmin_a_sclk_pre_en =
0492     AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
0493 static struct clk_regmap tdmin_b_sclk_pre_en =
0494     AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
0495 static struct clk_regmap tdmin_c_sclk_pre_en =
0496     AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
0497 static struct clk_regmap tdmin_lb_sclk_pre_en =
0498     AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
0499 static struct clk_regmap tdmout_a_sclk_pre_en =
0500     AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
0501 static struct clk_regmap tdmout_b_sclk_pre_en =
0502     AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
0503 static struct clk_regmap tdmout_c_sclk_pre_en =
0504     AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
0505
0506 static struct clk_regmap tdmin_a_sclk_post_en =
0507     AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
0508 static struct clk_regmap tdmin_b_sclk_post_en =
0509     AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
0510 static struct clk_regmap tdmin_c_sclk_post_en =
0511     AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
0512 static struct clk_regmap tdmin_lb_sclk_post_en =
0513     AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
0514 static struct clk_regmap tdmout_a_sclk_post_en =
0515     AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
0516 static struct clk_regmap tdmout_b_sclk_post_en =
0517     AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
0518 static struct clk_regmap tdmout_c_sclk_post_en =
0519     AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
0520
0521 static struct clk_regmap tdmin_a_sclk =
0522     AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
0523 static struct clk_regmap tdmin_b_sclk =
0524     AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
0525 static struct clk_regmap tdmin_c_sclk =
0526     AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
0527 static struct clk_regmap tdmin_lb_sclk =
0528     AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
0529
0530 static struct clk_regmap tdmin_a_lrclk =
0531     AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
0532 static struct clk_regmap tdmin_b_lrclk =
0533     AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
0534 static struct clk_regmap tdmin_c_lrclk =
0535     AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
0536 static struct clk_regmap tdmin_lb_lrclk =
0537     AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
0538 static struct clk_regmap tdmout_a_lrclk =
0539     AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
0540 static struct clk_regmap tdmout_b_lrclk =
0541     AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
0542 static struct clk_regmap tdmout_c_lrclk =
0543     AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
0544
0545 /* AXG Clocks */
0546 static struct clk_regmap axg_tdmout_a_sclk =
0547     AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
0548 static struct clk_regmap axg_tdmout_b_sclk =
0549     AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
0550 static struct clk_regmap axg_tdmout_c_sclk =
0551     AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
0552
0553 /* AXG/G12A Clocks */
0554 static struct clk_hw axg_aud_top = {
0555     .init = &(struct clk_init_data) {
0556         /* Provide aud_top signal name on axg and g12a */
0557         .name = "aud_top",
0558         .ops = &(const struct clk_ops) {},
0559         .parent_data = &(const struct clk_parent_data) {
0560             .fw_name = "pclk",
0561         },
0562         .num_parents = 1,
0563     },
0564 };
0565
0566 static struct clk_regmap mst_a_mclk_sel =
0567     AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
0568 static struct clk_regmap mst_b_mclk_sel =
0569     AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
0570 static struct clk_regmap mst_c_mclk_sel =
0571     AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
0572 static struct clk_regmap mst_d_mclk_sel =
0573     AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
0574 static struct clk_regmap mst_e_mclk_sel =
0575     AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
0576 static struct clk_regmap mst_f_mclk_sel =
0577     AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
0578
0579 static struct clk_regmap mst_a_mclk_div =
0580     AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
0581 static struct clk_regmap mst_b_mclk_div =
0582     AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
0583 static struct clk_regmap mst_c_mclk_div =
0584     AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
0585 static struct clk_regmap mst_d_mclk_div =
0586     AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
0587 static struct clk_regmap mst_e_mclk_div =
0588     AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
0589 static struct clk_regmap mst_f_mclk_div =
0590     AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
0591
0592 static struct clk_regmap mst_a_mclk =
0593     AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
0594 static struct clk_regmap mst_b_mclk =
0595     AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
0596 static struct clk_regmap mst_c_mclk =
0597     AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
0598 static struct clk_regmap mst_d_mclk =
0599     AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
0600 static struct clk_regmap mst_e_mclk =
0601     AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
0602 static struct clk_regmap mst_f_mclk =
0603     AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
0604
0605 /* G12a clocks */
0606 static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
0607     mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
0608 static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
0609     mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
0610 static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
0611     lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
0612 static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
0613     lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
0614 static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
0615     lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
0616 static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
0617     sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
0618 static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
0619     sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
0620 static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
0621     sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
0622
0623 static struct clk_regmap g12a_tdmout_a_sclk =
0624     AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
0625 static struct clk_regmap g12a_tdmout_b_sclk =
0626     AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
0627 static struct clk_regmap g12a_tdmout_c_sclk =
0628     AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
0629
0630 static struct clk_regmap toram =
0631     AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
0632 static struct clk_regmap spdifout_b =
0633     AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
0634 static struct clk_regmap eqdrc =
0635     AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
0636
0637 /* SM1 Clocks */
0638 static struct clk_regmap sm1_clk81_en = {
0639     .data = &(struct clk_regmap_gate_data){
0640         .offset = AUDIO_CLK81_EN,
0641         .bit_idx = 31,
0642     },
0643     .hw.init = &(struct clk_init_data) {
0644         .name = "aud_clk81_en",
0645         .ops = &clk_regmap_gate_ops,
0646         .parent_data = &(const struct clk_parent_data) {
0647             .fw_name = "pclk",
0648         },
0649         .num_parents = 1,
0650     },
0651 };
0652
0653 static struct clk_regmap sm1_sysclk_a_div = {
0654     .data = &(struct clk_regmap_div_data){
0655         .offset = AUDIO_CLK81_CTRL,
0656         .shift = 0,
0657         .width = 8,
0658     },
0659     .hw.init = &(struct clk_init_data) {
0660         .name = "aud_sysclk_a_div",
0661         .ops = &clk_regmap_divider_ops,
0662         .parent_hws = (const struct clk_hw *[]) {
0663             &sm1_clk81_en.hw,
0664         },
0665         .num_parents = 1,
0666         .flags = CLK_SET_RATE_PARENT,
0667     },
0668 };
0669
0670 static struct clk_regmap sm1_sysclk_a_en = {
0671     .data = &(struct clk_regmap_gate_data){
0672         .offset = AUDIO_CLK81_CTRL,
0673         .bit_idx = 8,
0674     },
0675     .hw.init = &(struct clk_init_data) {
0676         .name = "aud_sysclk_a_en",
0677         .ops = &clk_regmap_gate_ops,
0678         .parent_hws = (const struct clk_hw *[]) {
0679             &sm1_sysclk_a_div.hw,
0680         },
0681         .num_parents = 1,
0682         .flags = CLK_SET_RATE_PARENT,
0683     },
0684 };
0685
0686 static struct clk_regmap sm1_sysclk_b_div = {
0687     .data = &(struct clk_regmap_div_data){
0688         .offset = AUDIO_CLK81_CTRL,
0689         .shift = 16,
0690         .width = 8,
0691     },
0692     .hw.init = &(struct clk_init_data) {
0693         .name = "aud_sysclk_b_div",
0694         .ops = &clk_regmap_divider_ops,
0695         .parent_hws = (const struct clk_hw *[]) {
0696             &sm1_clk81_en.hw,
0697         },
0698         .num_parents = 1,
0699         .flags = CLK_SET_RATE_PARENT,
0700     },
0701 };
0702
0703 static struct clk_regmap sm1_sysclk_b_en = {
0704     .data = &(struct clk_regmap_gate_data){
0705         .offset = AUDIO_CLK81_CTRL,
0706         .bit_idx = 24,
0707     },
0708     .hw.init = &(struct clk_init_data) {
0709         .name = "aud_sysclk_b_en",
0710         .ops = &clk_regmap_gate_ops,
0711         .parent_hws = (const struct clk_hw *[]) {
0712             &sm1_sysclk_b_div.hw,
0713         },
0714         .num_parents = 1,
0715         .flags = CLK_SET_RATE_PARENT,
0716     },
0717 };
0718
0719 static const struct clk_hw *sm1_aud_top_parents[] = {
0720     &sm1_sysclk_a_en.hw,
0721     &sm1_sysclk_b_en.hw,
0722 };
0723
0724 static struct clk_regmap sm1_aud_top = {
0725     .data = &(struct clk_regmap_mux_data){
0726         .offset = AUDIO_CLK81_CTRL,
0727         .mask = 0x1,
0728         .shift = 31,
0729     },
0730     .hw.init = &(struct clk_init_data){
0731         .name = "aud_top",
0732         .ops = &clk_regmap_mux_ops,
0733         .parent_hws = sm1_aud_top_parents,
0734         .num_parents = ARRAY_SIZE(sm1_aud_top_parents),
0735         .flags = CLK_SET_RATE_NO_REPARENT,
0736     },
0737 };
0738
0739 static struct clk_regmap resample_b =
0740     AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
0741 static struct clk_regmap tovad =
0742     AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
0743 static struct clk_regmap locker =
0744     AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
0745 static struct clk_regmap spdifin_lb =
0746     AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
0747 static struct clk_regmap frddr_d =
0748     AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
0749 static struct clk_regmap toddr_d =
0750     AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
0751 static struct clk_regmap loopback_b =
0752     AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
0753
0754 static struct clk_regmap sm1_mst_a_mclk_sel =
0755     AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
0756 static struct clk_regmap sm1_mst_b_mclk_sel =
0757     AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
0758 static struct clk_regmap sm1_mst_c_mclk_sel =
0759     AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
0760 static struct clk_regmap sm1_mst_d_mclk_sel =
0761     AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
0762 static struct clk_regmap sm1_mst_e_mclk_sel =
0763     AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
0764 static struct clk_regmap sm1_mst_f_mclk_sel =
0765     AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
0766
0767 static struct clk_regmap sm1_mst_a_mclk_div =
0768     AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
0769 static struct clk_regmap sm1_mst_b_mclk_div =
0770     AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
0771 static struct clk_regmap sm1_mst_c_mclk_div =
0772     AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
0773 static struct clk_regmap sm1_mst_d_mclk_div =
0774     AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
0775 static struct clk_regmap sm1_mst_e_mclk_div =
0776     AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
0777 static struct clk_regmap sm1_mst_f_mclk_div =
0778     AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
0779
0780 static struct clk_regmap sm1_mst_a_mclk =
0781     AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
0782 static struct clk_regmap sm1_mst_b_mclk =
0783     AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
0784 static struct clk_regmap sm1_mst_c_mclk =
0785     AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
0786 static struct clk_regmap sm1_mst_d_mclk =
0787     AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
0788 static struct clk_regmap sm1_mst_e_mclk =
0789     AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
0790 static struct clk_regmap sm1_mst_f_mclk =
0791     AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
0792
0793 static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
0794     tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
0795 static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
0796     tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
0797 static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
0798     tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
0799 static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
0800     tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
0801 static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
0802     tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
0803 static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
0804     tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
0805 static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
0806     tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
0807 static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
0808     tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
0809
0810 /*
0811  * Array of all clocks provided by this provider
0812  * The input clocks of the controller will be populated at runtime
0813  */
0814 static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
0815     .hws = {
0816         [AUD_CLKID_DDR_ARB]     = &ddr_arb.hw,
0817         [AUD_CLKID_PDM]         = &pdm.hw,
0818         [AUD_CLKID_TDMIN_A]     = &tdmin_a.hw,
0819         [AUD_CLKID_TDMIN_B]     = &tdmin_b.hw,
0820         [AUD_CLKID_TDMIN_C]     = &tdmin_c.hw,
0821         [AUD_CLKID_TDMIN_LB]        = &tdmin_lb.hw,
0822         [AUD_CLKID_TDMOUT_A]        = &tdmout_a.hw,
0823         [AUD_CLKID_TDMOUT_B]        = &tdmout_b.hw,
0824         [AUD_CLKID_TDMOUT_C]        = &tdmout_c.hw,
0825         [AUD_CLKID_FRDDR_A]     = &frddr_a.hw,
0826         [AUD_CLKID_FRDDR_B]     = &frddr_b.hw,
0827         [AUD_CLKID_FRDDR_C]     = &frddr_c.hw,
0828         [AUD_CLKID_TODDR_A]     = &toddr_a.hw,
0829         [AUD_CLKID_TODDR_B]     = &toddr_b.hw,
0830         [AUD_CLKID_TODDR_C]     = &toddr_c.hw,
0831         [AUD_CLKID_LOOPBACK]        = &loopback.hw,
0832         [AUD_CLKID_SPDIFIN]     = &spdifin.hw,
0833         [AUD_CLKID_SPDIFOUT]        = &spdifout.hw,
0834         [AUD_CLKID_RESAMPLE]        = &resample.hw,
0835         [AUD_CLKID_POWER_DETECT]    = &power_detect.hw,
0836         [AUD_CLKID_MST_A_MCLK_SEL]  = &mst_a_mclk_sel.hw,
0837         [AUD_CLKID_MST_B_MCLK_SEL]  = &mst_b_mclk_sel.hw,
0838         [AUD_CLKID_MST_C_MCLK_SEL]  = &mst_c_mclk_sel.hw,
0839         [AUD_CLKID_MST_D_MCLK_SEL]  = &mst_d_mclk_sel.hw,
0840         [AUD_CLKID_MST_E_MCLK_SEL]  = &mst_e_mclk_sel.hw,
0841         [AUD_CLKID_MST_F_MCLK_SEL]  = &mst_f_mclk_sel.hw,
0842         [AUD_CLKID_MST_A_MCLK_DIV]  = &mst_a_mclk_div.hw,
0843         [AUD_CLKID_MST_B_MCLK_DIV]  = &mst_b_mclk_div.hw,
0844         [AUD_CLKID_MST_C_MCLK_DIV]  = &mst_c_mclk_div.hw,
0845         [AUD_CLKID_MST_D_MCLK_DIV]  = &mst_d_mclk_div.hw,
0846         [AUD_CLKID_MST_E_MCLK_DIV]  = &mst_e_mclk_div.hw,
0847         [AUD_CLKID_MST_F_MCLK_DIV]  = &mst_f_mclk_div.hw,
0848         [AUD_CLKID_MST_A_MCLK]      = &mst_a_mclk.hw,
0849         [AUD_CLKID_MST_B_MCLK]      = &mst_b_mclk.hw,
0850         [AUD_CLKID_MST_C_MCLK]      = &mst_c_mclk.hw,
0851         [AUD_CLKID_MST_D_MCLK]      = &mst_d_mclk.hw,
0852         [AUD_CLKID_MST_E_MCLK]      = &mst_e_mclk.hw,
0853         [AUD_CLKID_MST_F_MCLK]      = &mst_f_mclk.hw,
0854         [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
0855         [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
0856         [AUD_CLKID_SPDIFOUT_CLK]    = &spdifout_clk.hw,
0857         [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
0858         [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
0859         [AUD_CLKID_SPDIFIN_CLK]     = &spdifin_clk.hw,
0860         [AUD_CLKID_PDM_DCLK_SEL]    = &pdm_dclk_sel.hw,
0861         [AUD_CLKID_PDM_DCLK_DIV]    = &pdm_dclk_div.hw,
0862         [AUD_CLKID_PDM_DCLK]        = &pdm_dclk.hw,
0863         [AUD_CLKID_PDM_SYSCLK_SEL]  = &pdm_sysclk_sel.hw,
0864         [AUD_CLKID_PDM_SYSCLK_DIV]  = &pdm_sysclk_div.hw,
0865         [AUD_CLKID_PDM_SYSCLK]      = &pdm_sysclk.hw,
0866         [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
0867         [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
0868         [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
0869         [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
0870         [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
0871         [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
0872         [AUD_CLKID_MST_A_SCLK_DIV]  = &mst_a_sclk_div.hw,
0873         [AUD_CLKID_MST_B_SCLK_DIV]  = &mst_b_sclk_div.hw,
0874         [AUD_CLKID_MST_C_SCLK_DIV]  = &mst_c_sclk_div.hw,
0875         [AUD_CLKID_MST_D_SCLK_DIV]  = &mst_d_sclk_div.hw,
0876         [AUD_CLKID_MST_E_SCLK_DIV]  = &mst_e_sclk_div.hw,
0877         [AUD_CLKID_MST_F_SCLK_DIV]  = &mst_f_sclk_div.hw,
0878         [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
0879         [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
0880         [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
0881         [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
0882         [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
0883         [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
0884         [AUD_CLKID_MST_A_SCLK]      = &mst_a_sclk.hw,
0885         [AUD_CLKID_MST_B_SCLK]      = &mst_b_sclk.hw,
0886         [AUD_CLKID_MST_C_SCLK]      = &mst_c_sclk.hw,
0887         [AUD_CLKID_MST_D_SCLK]      = &mst_d_sclk.hw,
0888         [AUD_CLKID_MST_E_SCLK]      = &mst_e_sclk.hw,
0889         [AUD_CLKID_MST_F_SCLK]      = &mst_f_sclk.hw,
0890         [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
0891         [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
0892         [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
0893         [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
0894         [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
0895         [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
0896         [AUD_CLKID_MST_A_LRCLK]     = &mst_a_lrclk.hw,
0897         [AUD_CLKID_MST_B_LRCLK]     = &mst_b_lrclk.hw,
0898         [AUD_CLKID_MST_C_LRCLK]     = &mst_c_lrclk.hw,
0899         [AUD_CLKID_MST_D_LRCLK]     = &mst_d_lrclk.hw,
0900         [AUD_CLKID_MST_E_LRCLK]     = &mst_e_lrclk.hw,
0901         [AUD_CLKID_MST_F_LRCLK]     = &mst_f_lrclk.hw,
0902         [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
0903         [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
0904         [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
0905         [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
0906         [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
0907         [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
0908         [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
0909         [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
0910         [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
0911         [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
0912         [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
0913         [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
0914         [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
0915         [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
0916         [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
0917         [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
0918         [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
0919         [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
0920         [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
0921         [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
0922         [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
0923         [AUD_CLKID_TDMIN_A_SCLK]    = &tdmin_a_sclk.hw,
0924         [AUD_CLKID_TDMIN_B_SCLK]    = &tdmin_b_sclk.hw,
0925         [AUD_CLKID_TDMIN_C_SCLK]    = &tdmin_c_sclk.hw,
0926         [AUD_CLKID_TDMIN_LB_SCLK]   = &tdmin_lb_sclk.hw,
0927         [AUD_CLKID_TDMOUT_A_SCLK]   = &axg_tdmout_a_sclk.hw,
0928         [AUD_CLKID_TDMOUT_B_SCLK]   = &axg_tdmout_b_sclk.hw,
0929         [AUD_CLKID_TDMOUT_C_SCLK]   = &axg_tdmout_c_sclk.hw,
0930         [AUD_CLKID_TDMIN_A_LRCLK]   = &tdmin_a_lrclk.hw,
0931         [AUD_CLKID_TDMIN_B_LRCLK]   = &tdmin_b_lrclk.hw,
0932         [AUD_CLKID_TDMIN_C_LRCLK]   = &tdmin_c_lrclk.hw,
0933         [AUD_CLKID_TDMIN_LB_LRCLK]  = &tdmin_lb_lrclk.hw,
0934         [AUD_CLKID_TDMOUT_A_LRCLK]  = &tdmout_a_lrclk.hw,
0935         [AUD_CLKID_TDMOUT_B_LRCLK]  = &tdmout_b_lrclk.hw,
0936         [AUD_CLKID_TDMOUT_C_LRCLK]  = &tdmout_c_lrclk.hw,
0937         [AUD_CLKID_TOP]         = &axg_aud_top,
0938         [NR_CLKS] = NULL,
0939     },
0940     .num = NR_CLKS,
0941 };
0942
0943 /*
0944  * Array of all G12A clocks provided by this provider
0945  * The input clocks of the controller will be populated at runtime
0946  */
0947 static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
0948     .hws = {
0949         [AUD_CLKID_DDR_ARB]     = &ddr_arb.hw,
0950         [AUD_CLKID_PDM]         = &pdm.hw,
0951         [AUD_CLKID_TDMIN_A]     = &tdmin_a.hw,
0952         [AUD_CLKID_TDMIN_B]     = &tdmin_b.hw,
0953         [AUD_CLKID_TDMIN_C]     = &tdmin_c.hw,
0954         [AUD_CLKID_TDMIN_LB]        = &tdmin_lb.hw,
0955         [AUD_CLKID_TDMOUT_A]        = &tdmout_a.hw,
0956         [AUD_CLKID_TDMOUT_B]        = &tdmout_b.hw,
0957         [AUD_CLKID_TDMOUT_C]        = &tdmout_c.hw,
0958         [AUD_CLKID_FRDDR_A]     = &frddr_a.hw,
0959         [AUD_CLKID_FRDDR_B]     = &frddr_b.hw,
0960         [AUD_CLKID_FRDDR_C]     = &frddr_c.hw,
0961         [AUD_CLKID_TODDR_A]     = &toddr_a.hw,
0962         [AUD_CLKID_TODDR_B]     = &toddr_b.hw,
0963         [AUD_CLKID_TODDR_C]     = &toddr_c.hw,
0964         [AUD_CLKID_LOOPBACK]        = &loopback.hw,
0965         [AUD_CLKID_SPDIFIN]     = &spdifin.hw,
0966         [AUD_CLKID_SPDIFOUT]        = &spdifout.hw,
0967         [AUD_CLKID_RESAMPLE]        = &resample.hw,
0968         [AUD_CLKID_POWER_DETECT]    = &power_detect.hw,
0969         [AUD_CLKID_SPDIFOUT_B]      = &spdifout_b.hw,
0970         [AUD_CLKID_MST_A_MCLK_SEL]  = &mst_a_mclk_sel.hw,
0971         [AUD_CLKID_MST_B_MCLK_SEL]  = &mst_b_mclk_sel.hw,
0972         [AUD_CLKID_MST_C_MCLK_SEL]  = &mst_c_mclk_sel.hw,
0973         [AUD_CLKID_MST_D_MCLK_SEL]  = &mst_d_mclk_sel.hw,
0974         [AUD_CLKID_MST_E_MCLK_SEL]  = &mst_e_mclk_sel.hw,
0975         [AUD_CLKID_MST_F_MCLK_SEL]  = &mst_f_mclk_sel.hw,
0976         [AUD_CLKID_MST_A_MCLK_DIV]  = &mst_a_mclk_div.hw,
0977         [AUD_CLKID_MST_B_MCLK_DIV]  = &mst_b_mclk_div.hw,
0978         [AUD_CLKID_MST_C_MCLK_DIV]  = &mst_c_mclk_div.hw,
0979         [AUD_CLKID_MST_D_MCLK_DIV]  = &mst_d_mclk_div.hw,
0980         [AUD_CLKID_MST_E_MCLK_DIV]  = &mst_e_mclk_div.hw,
0981         [AUD_CLKID_MST_F_MCLK_DIV]  = &mst_f_mclk_div.hw,
0982         [AUD_CLKID_MST_A_MCLK]      = &mst_a_mclk.hw,
0983         [AUD_CLKID_MST_B_MCLK]      = &mst_b_mclk.hw,
0984         [AUD_CLKID_MST_C_MCLK]      = &mst_c_mclk.hw,
0985         [AUD_CLKID_MST_D_MCLK]      = &mst_d_mclk.hw,
0986         [AUD_CLKID_MST_E_MCLK]      = &mst_e_mclk.hw,
0987         [AUD_CLKID_MST_F_MCLK]      = &mst_f_mclk.hw,
0988         [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
0989         [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
0990         [AUD_CLKID_SPDIFOUT_CLK]    = &spdifout_clk.hw,
0991         [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &spdifout_b_clk_sel.hw,
0992         [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &spdifout_b_clk_div.hw,
0993         [AUD_CLKID_SPDIFOUT_B_CLK]  = &spdifout_b_clk.hw,
0994         [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
0995         [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
0996         [AUD_CLKID_SPDIFIN_CLK]     = &spdifin_clk.hw,
0997         [AUD_CLKID_PDM_DCLK_SEL]    = &pdm_dclk_sel.hw,
0998         [AUD_CLKID_PDM_DCLK_DIV]    = &pdm_dclk_div.hw,
0999         [AUD_CLKID_PDM_DCLK]        = &pdm_dclk.hw,
1000         [AUD_CLKID_PDM_SYSCLK_SEL]  = &pdm_sysclk_sel.hw,
1001         [AUD_CLKID_PDM_SYSCLK_DIV]  = &pdm_sysclk_div.hw,
1002         [AUD_CLKID_PDM_SYSCLK]      = &pdm_sysclk.hw,
1003         [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
1004         [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
1005         [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
1006         [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
1007         [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
1008         [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
1009         [AUD_CLKID_MST_A_SCLK_DIV]  = &mst_a_sclk_div.hw,
1010         [AUD_CLKID_MST_B_SCLK_DIV]  = &mst_b_sclk_div.hw,
1011         [AUD_CLKID_MST_C_SCLK_DIV]  = &mst_c_sclk_div.hw,
1012         [AUD_CLKID_MST_D_SCLK_DIV]  = &mst_d_sclk_div.hw,
1013         [AUD_CLKID_MST_E_SCLK_DIV]  = &mst_e_sclk_div.hw,
1014         [AUD_CLKID_MST_F_SCLK_DIV]  = &mst_f_sclk_div.hw,
1015         [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
1016         [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
1017         [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
1018         [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
1019         [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
1020         [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
1021         [AUD_CLKID_MST_A_SCLK]      = &mst_a_sclk.hw,
1022         [AUD_CLKID_MST_B_SCLK]      = &mst_b_sclk.hw,
1023         [AUD_CLKID_MST_C_SCLK]      = &mst_c_sclk.hw,
1024         [AUD_CLKID_MST_D_SCLK]      = &mst_d_sclk.hw,
1025         [AUD_CLKID_MST_E_SCLK]      = &mst_e_sclk.hw,
1026         [AUD_CLKID_MST_F_SCLK]      = &mst_f_sclk.hw,
1027         [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1028         [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1029         [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1030         [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1031         [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1032         [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1033         [AUD_CLKID_MST_A_LRCLK]     = &mst_a_lrclk.hw,
1034         [AUD_CLKID_MST_B_LRCLK]     = &mst_b_lrclk.hw,
1035         [AUD_CLKID_MST_C_LRCLK]     = &mst_c_lrclk.hw,
1036         [AUD_CLKID_MST_D_LRCLK]     = &mst_d_lrclk.hw,
1037         [AUD_CLKID_MST_E_LRCLK]     = &mst_e_lrclk.hw,
1038         [AUD_CLKID_MST_F_LRCLK]     = &mst_f_lrclk.hw,
1039         [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
1040         [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
1041         [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
1042         [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
1043         [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
1044         [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
1045         [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
1046         [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1047         [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1048         [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1049         [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1050         [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1051         [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1052         [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1053         [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1054         [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1055         [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1056         [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1057         [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1058         [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1059         [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1060         [AUD_CLKID_TDMIN_A_SCLK]    = &tdmin_a_sclk.hw,
1061         [AUD_CLKID_TDMIN_B_SCLK]    = &tdmin_b_sclk.hw,
1062         [AUD_CLKID_TDMIN_C_SCLK]    = &tdmin_c_sclk.hw,
1063         [AUD_CLKID_TDMIN_LB_SCLK]   = &tdmin_lb_sclk.hw,
1064         [AUD_CLKID_TDMOUT_A_SCLK]   = &g12a_tdmout_a_sclk.hw,
1065         [AUD_CLKID_TDMOUT_B_SCLK]   = &g12a_tdmout_b_sclk.hw,
1066         [AUD_CLKID_TDMOUT_C_SCLK]   = &g12a_tdmout_c_sclk.hw,
1067         [AUD_CLKID_TDMIN_A_LRCLK]   = &tdmin_a_lrclk.hw,
1068         [AUD_CLKID_TDMIN_B_LRCLK]   = &tdmin_b_lrclk.hw,
1069         [AUD_CLKID_TDMIN_C_LRCLK]   = &tdmin_c_lrclk.hw,
1070         [AUD_CLKID_TDMIN_LB_LRCLK]  = &tdmin_lb_lrclk.hw,
1071         [AUD_CLKID_TDMOUT_A_LRCLK]  = &tdmout_a_lrclk.hw,
1072         [AUD_CLKID_TDMOUT_B_LRCLK]  = &tdmout_b_lrclk.hw,
1073         [AUD_CLKID_TDMOUT_C_LRCLK]  = &tdmout_c_lrclk.hw,
1074         [AUD_CLKID_TDM_MCLK_PAD0]   = &g12a_tdm_mclk_pad_0.hw,
1075         [AUD_CLKID_TDM_MCLK_PAD1]   = &g12a_tdm_mclk_pad_1.hw,
1076         [AUD_CLKID_TDM_LRCLK_PAD0]  = &g12a_tdm_lrclk_pad_0.hw,
1077         [AUD_CLKID_TDM_LRCLK_PAD1]  = &g12a_tdm_lrclk_pad_1.hw,
1078         [AUD_CLKID_TDM_LRCLK_PAD2]  = &g12a_tdm_lrclk_pad_2.hw,
1079         [AUD_CLKID_TDM_SCLK_PAD0]   = &g12a_tdm_sclk_pad_0.hw,
1080         [AUD_CLKID_TDM_SCLK_PAD1]   = &g12a_tdm_sclk_pad_1.hw,
1081         [AUD_CLKID_TDM_SCLK_PAD2]   = &g12a_tdm_sclk_pad_2.hw,
1082         [AUD_CLKID_TOP]         = &axg_aud_top,
1083         [NR_CLKS] = NULL,
1084     },
1085     .num = NR_CLKS,
1086 };
1087
1088 /*
1089  * Array of all SM1 clocks provided by this provider
1090  * The input clocks of the controller will be populated at runtime
1091  */
1092 static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
1093     .hws = {
1094         [AUD_CLKID_DDR_ARB]     = &ddr_arb.hw,
1095         [AUD_CLKID_PDM]         = &pdm.hw,
1096         [AUD_CLKID_TDMIN_A]     = &tdmin_a.hw,
1097         [AUD_CLKID_TDMIN_B]     = &tdmin_b.hw,
1098         [AUD_CLKID_TDMIN_C]     = &tdmin_c.hw,
1099         [AUD_CLKID_TDMIN_LB]        = &tdmin_lb.hw,
1100         [AUD_CLKID_TDMOUT_A]        = &tdmout_a.hw,
1101         [AUD_CLKID_TDMOUT_B]        = &tdmout_b.hw,
1102         [AUD_CLKID_TDMOUT_C]        = &tdmout_c.hw,
1103         [AUD_CLKID_FRDDR_A]     = &frddr_a.hw,
1104         [AUD_CLKID_FRDDR_B]     = &frddr_b.hw,
1105         [AUD_CLKID_FRDDR_C]     = &frddr_c.hw,
1106         [AUD_CLKID_TODDR_A]     = &toddr_a.hw,
1107         [AUD_CLKID_TODDR_B]     = &toddr_b.hw,
1108         [AUD_CLKID_TODDR_C]     = &toddr_c.hw,
1109         [AUD_CLKID_LOOPBACK]        = &loopback.hw,
1110         [AUD_CLKID_SPDIFIN]     = &spdifin.hw,
1111         [AUD_CLKID_SPDIFOUT]        = &spdifout.hw,
1112         [AUD_CLKID_RESAMPLE]        = &resample.hw,
1113         [AUD_CLKID_SPDIFOUT_B]      = &spdifout_b.hw,
1114         [AUD_CLKID_MST_A_MCLK_SEL]  = &sm1_mst_a_mclk_sel.hw,
1115         [AUD_CLKID_MST_B_MCLK_SEL]  = &sm1_mst_b_mclk_sel.hw,
1116         [AUD_CLKID_MST_C_MCLK_SEL]  = &sm1_mst_c_mclk_sel.hw,
1117         [AUD_CLKID_MST_D_MCLK_SEL]  = &sm1_mst_d_mclk_sel.hw,
1118         [AUD_CLKID_MST_E_MCLK_SEL]  = &sm1_mst_e_mclk_sel.hw,
1119         [AUD_CLKID_MST_F_MCLK_SEL]  = &sm1_mst_f_mclk_sel.hw,
1120         [AUD_CLKID_MST_A_MCLK_DIV]  = &sm1_mst_a_mclk_div.hw,
1121         [AUD_CLKID_MST_B_MCLK_DIV]  = &sm1_mst_b_mclk_div.hw,
1122         [AUD_CLKID_MST_C_MCLK_DIV]  = &sm1_mst_c_mclk_div.hw,
1123         [AUD_CLKID_MST_D_MCLK_DIV]  = &sm1_mst_d_mclk_div.hw,
1124         [AUD_CLKID_MST_E_MCLK_DIV]  = &sm1_mst_e_mclk_div.hw,
1125         [AUD_CLKID_MST_F_MCLK_DIV]  = &sm1_mst_f_mclk_div.hw,
1126         [AUD_CLKID_MST_A_MCLK]      = &sm1_mst_a_mclk.hw,
1127         [AUD_CLKID_MST_B_MCLK]      = &sm1_mst_b_mclk.hw,
1128         [AUD_CLKID_MST_C_MCLK]      = &sm1_mst_c_mclk.hw,
1129         [AUD_CLKID_MST_D_MCLK]      = &sm1_mst_d_mclk.hw,
1130         [AUD_CLKID_MST_E_MCLK]      = &sm1_mst_e_mclk.hw,
1131         [AUD_CLKID_MST_F_MCLK]      = &sm1_mst_f_mclk.hw,
1132         [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
1133         [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
1134         [AUD_CLKID_SPDIFOUT_CLK]    = &spdifout_clk.hw,
1135         [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &spdifout_b_clk_sel.hw,
1136         [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &spdifout_b_clk_div.hw,
1137         [AUD_CLKID_SPDIFOUT_B_CLK]  = &spdifout_b_clk.hw,
1138         [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1139         [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1140         [AUD_CLKID_SPDIFIN_CLK]     = &spdifin_clk.hw,
1141         [AUD_CLKID_PDM_DCLK_SEL]    = &pdm_dclk_sel.hw,
1142         [AUD_CLKID_PDM_DCLK_DIV]    = &pdm_dclk_div.hw,
1143         [AUD_CLKID_PDM_DCLK]        = &pdm_dclk.hw,
1144         [AUD_CLKID_PDM_SYSCLK_SEL]  = &pdm_sysclk_sel.hw,
1145         [AUD_CLKID_PDM_SYSCLK_DIV]  = &pdm_sysclk_div.hw,
1146         [AUD_CLKID_PDM_SYSCLK]      = &pdm_sysclk.hw,
1147         [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
1148         [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
1149         [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
1150         [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
1151         [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
1152         [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
1153         [AUD_CLKID_MST_A_SCLK_DIV]  = &mst_a_sclk_div.hw,
1154         [AUD_CLKID_MST_B_SCLK_DIV]  = &mst_b_sclk_div.hw,
1155         [AUD_CLKID_MST_C_SCLK_DIV]  = &mst_c_sclk_div.hw,
1156         [AUD_CLKID_MST_D_SCLK_DIV]  = &mst_d_sclk_div.hw,
1157         [AUD_CLKID_MST_E_SCLK_DIV]  = &mst_e_sclk_div.hw,
1158         [AUD_CLKID_MST_F_SCLK_DIV]  = &mst_f_sclk_div.hw,
1159         [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
1160         [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
1161         [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
1162         [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
1163         [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
1164         [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
1165         [AUD_CLKID_MST_A_SCLK]      = &mst_a_sclk.hw,
1166         [AUD_CLKID_MST_B_SCLK]      = &mst_b_sclk.hw,
1167         [AUD_CLKID_MST_C_SCLK]      = &mst_c_sclk.hw,
1168         [AUD_CLKID_MST_D_SCLK]      = &mst_d_sclk.hw,
1169         [AUD_CLKID_MST_E_SCLK]      = &mst_e_sclk.hw,
1170         [AUD_CLKID_MST_F_SCLK]      = &mst_f_sclk.hw,
1171         [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1172         [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1173         [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1174         [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1175         [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1176         [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1177         [AUD_CLKID_MST_A_LRCLK]     = &mst_a_lrclk.hw,
1178         [AUD_CLKID_MST_B_LRCLK]     = &mst_b_lrclk.hw,
1179         [AUD_CLKID_MST_C_LRCLK]     = &mst_c_lrclk.hw,
1180         [AUD_CLKID_MST_D_LRCLK]     = &mst_d_lrclk.hw,
1181         [AUD_CLKID_MST_E_LRCLK]     = &mst_e_lrclk.hw,
1182         [AUD_CLKID_MST_F_LRCLK]     = &mst_f_lrclk.hw,
1183         [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
1184         [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
1185         [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
1186         [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
1187         [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
1188         [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
1189         [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
1190         [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1191         [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1192         [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1193         [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1194         [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1195         [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1196         [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1197         [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1198         [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1199         [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1200         [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1201         [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1202         [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1203         [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1204         [AUD_CLKID_TDMIN_A_SCLK]    = &tdmin_a_sclk.hw,
1205         [AUD_CLKID_TDMIN_B_SCLK]    = &tdmin_b_sclk.hw,
1206         [AUD_CLKID_TDMIN_C_SCLK]    = &tdmin_c_sclk.hw,
1207         [AUD_CLKID_TDMIN_LB_SCLK]   = &tdmin_lb_sclk.hw,
1208         [AUD_CLKID_TDMOUT_A_SCLK]   = &g12a_tdmout_a_sclk.hw,
1209         [AUD_CLKID_TDMOUT_B_SCLK]   = &g12a_tdmout_b_sclk.hw,
1210         [AUD_CLKID_TDMOUT_C_SCLK]   = &g12a_tdmout_c_sclk.hw,
1211         [AUD_CLKID_TDMIN_A_LRCLK]   = &tdmin_a_lrclk.hw,
1212         [AUD_CLKID_TDMIN_B_LRCLK]   = &tdmin_b_lrclk.hw,
1213         [AUD_CLKID_TDMIN_C_LRCLK]   = &tdmin_c_lrclk.hw,
1214         [AUD_CLKID_TDMIN_LB_LRCLK]  = &tdmin_lb_lrclk.hw,
1215         [AUD_CLKID_TDMOUT_A_LRCLK]  = &tdmout_a_lrclk.hw,
1216         [AUD_CLKID_TDMOUT_B_LRCLK]  = &tdmout_b_lrclk.hw,
1217         [AUD_CLKID_TDMOUT_C_LRCLK]  = &tdmout_c_lrclk.hw,
1218         [AUD_CLKID_TDM_MCLK_PAD0]   = &sm1_tdm_mclk_pad_0.hw,
1219         [AUD_CLKID_TDM_MCLK_PAD1]   = &sm1_tdm_mclk_pad_1.hw,
1220         [AUD_CLKID_TDM_LRCLK_PAD0]  = &sm1_tdm_lrclk_pad_0.hw,
1221         [AUD_CLKID_TDM_LRCLK_PAD1]  = &sm1_tdm_lrclk_pad_1.hw,
1222         [AUD_CLKID_TDM_LRCLK_PAD2]  = &sm1_tdm_lrclk_pad_2.hw,
1223         [AUD_CLKID_TDM_SCLK_PAD0]   = &sm1_tdm_sclk_pad_0.hw,
1224         [AUD_CLKID_TDM_SCLK_PAD1]   = &sm1_tdm_sclk_pad_1.hw,
1225         [AUD_CLKID_TDM_SCLK_PAD2]   = &sm1_tdm_sclk_pad_2.hw,
1226         [AUD_CLKID_TOP]         = &sm1_aud_top.hw,
1227         [AUD_CLKID_TORAM]       = &toram.hw,
1228         [AUD_CLKID_EQDRC]       = &eqdrc.hw,
1229         [AUD_CLKID_RESAMPLE_B]      = &resample_b.hw,
1230         [AUD_CLKID_TOVAD]       = &tovad.hw,
1231         [AUD_CLKID_LOCKER]      = &locker.hw,
1232         [AUD_CLKID_SPDIFIN_LB]      = &spdifin_lb.hw,
1233         [AUD_CLKID_FRDDR_D]     = &frddr_d.hw,
1234         [AUD_CLKID_TODDR_D]     = &toddr_d.hw,
1235         [AUD_CLKID_LOOPBACK_B]      = &loopback_b.hw,
1236         [AUD_CLKID_CLK81_EN]        = &sm1_clk81_en.hw,
1237         [AUD_CLKID_SYSCLK_A_DIV]    = &sm1_sysclk_a_div.hw,
1238         [AUD_CLKID_SYSCLK_A_EN]     = &sm1_sysclk_a_en.hw,
1239         [AUD_CLKID_SYSCLK_B_DIV]    = &sm1_sysclk_b_div.hw,
1240         [AUD_CLKID_SYSCLK_B_EN]     = &sm1_sysclk_b_en.hw,
1241         [NR_CLKS] = NULL,
1242     },
1243     .num = NR_CLKS,
1244 };
1245
1246
1247 /* Convenience table to populate regmap in .probe(). */
1248 static struct clk_regmap *const axg_clk_regmaps[] = {
1249     &ddr_arb,
1250     &pdm,
1251     &tdmin_a,
1252     &tdmin_b,
1253     &tdmin_c,
1254     &tdmin_lb,
1255     &tdmout_a,
1256     &tdmout_b,
1257     &tdmout_c,
1258     &frddr_a,
1259     &frddr_b,
1260     &frddr_c,
1261     &toddr_a,
1262     &toddr_b,
1263     &toddr_c,
1264     &loopback,
1265     &spdifin,
1266     &spdifout,
1267     &resample,
1268     &power_detect,
1269     &mst_a_mclk_sel,
1270     &mst_b_mclk_sel,
1271     &mst_c_mclk_sel,
1272     &mst_d_mclk_sel,
1273     &mst_e_mclk_sel,
1274     &mst_f_mclk_sel,
1275     &mst_a_mclk_div,
1276     &mst_b_mclk_div,
1277     &mst_c_mclk_div,
1278     &mst_d_mclk_div,
1279     &mst_e_mclk_div,
1280     &mst_f_mclk_div,
1281     &mst_a_mclk,
1282     &mst_b_mclk,
1283     &mst_c_mclk,
1284     &mst_d_mclk,
1285     &mst_e_mclk,
1286     &mst_f_mclk,
1287     &spdifout_clk_sel,
1288     &spdifout_clk_div,
1289     &spdifout_clk,
1290     &spdifin_clk_sel,
1291     &spdifin_clk_div,
1292     &spdifin_clk,
1293     &pdm_dclk_sel,
1294     &pdm_dclk_div,
1295     &pdm_dclk,
1296     &pdm_sysclk_sel,
1297     &pdm_sysclk_div,
1298     &pdm_sysclk,
1299     &mst_a_sclk_pre_en,
1300     &mst_b_sclk_pre_en,
1301     &mst_c_sclk_pre_en,
1302     &mst_d_sclk_pre_en,
1303     &mst_e_sclk_pre_en,
1304     &mst_f_sclk_pre_en,
1305     &mst_a_sclk_div,
1306     &mst_b_sclk_div,
1307     &mst_c_sclk_div,
1308     &mst_d_sclk_div,
1309     &mst_e_sclk_div,
1310     &mst_f_sclk_div,
1311     &mst_a_sclk_post_en,
1312     &mst_b_sclk_post_en,
1313     &mst_c_sclk_post_en,
1314     &mst_d_sclk_post_en,
1315     &mst_e_sclk_post_en,
1316     &mst_f_sclk_post_en,
1317     &mst_a_sclk,
1318     &mst_b_sclk,
1319     &mst_c_sclk,
1320     &mst_d_sclk,
1321     &mst_e_sclk,
1322     &mst_f_sclk,
1323     &mst_a_lrclk_div,
1324     &mst_b_lrclk_div,
1325     &mst_c_lrclk_div,
1326     &mst_d_lrclk_div,
1327     &mst_e_lrclk_div,
1328     &mst_f_lrclk_div,
1329     &mst_a_lrclk,
1330     &mst_b_lrclk,
1331     &mst_c_lrclk,
1332     &mst_d_lrclk,
1333     &mst_e_lrclk,
1334     &mst_f_lrclk,
1335     &tdmin_a_sclk_sel,
1336     &tdmin_b_sclk_sel,
1337     &tdmin_c_sclk_sel,
1338     &tdmin_lb_sclk_sel,
1339     &tdmout_a_sclk_sel,
1340     &tdmout_b_sclk_sel,
1341     &tdmout_c_sclk_sel,
1342     &tdmin_a_sclk_pre_en,
1343     &tdmin_b_sclk_pre_en,
1344     &tdmin_c_sclk_pre_en,
1345     &tdmin_lb_sclk_pre_en,
1346     &tdmout_a_sclk_pre_en,
1347     &tdmout_b_sclk_pre_en,
1348     &tdmout_c_sclk_pre_en,
1349     &tdmin_a_sclk_post_en,
1350     &tdmin_b_sclk_post_en,
1351     &tdmin_c_sclk_post_en,
1352     &tdmin_lb_sclk_post_en,
1353     &tdmout_a_sclk_post_en,
1354     &tdmout_b_sclk_post_en,
1355     &tdmout_c_sclk_post_en,
1356     &tdmin_a_sclk,
1357     &tdmin_b_sclk,
1358     &tdmin_c_sclk,
1359     &tdmin_lb_sclk,
1360     &axg_tdmout_a_sclk,
1361     &axg_tdmout_b_sclk,
1362     &axg_tdmout_c_sclk,
1363     &tdmin_a_lrclk,
1364     &tdmin_b_lrclk,
1365     &tdmin_c_lrclk,
1366     &tdmin_lb_lrclk,
1367     &tdmout_a_lrclk,
1368     &tdmout_b_lrclk,
1369     &tdmout_c_lrclk,
1370 };
1371
1372 static struct clk_regmap *const g12a_clk_regmaps[] = {
1373     &ddr_arb,
1374     &pdm,
1375     &tdmin_a,
1376     &tdmin_b,
1377     &tdmin_c,
1378     &tdmin_lb,
1379     &tdmout_a,
1380     &tdmout_b,
1381     &tdmout_c,
1382     &frddr_a,
1383     &frddr_b,
1384     &frddr_c,
1385     &toddr_a,
1386     &toddr_b,
1387     &toddr_c,
1388     &loopback,
1389     &spdifin,
1390     &spdifout,
1391     &resample,
1392     &power_detect,
1393     &spdifout_b,
1394     &mst_a_mclk_sel,
1395     &mst_b_mclk_sel,
1396     &mst_c_mclk_sel,
1397     &mst_d_mclk_sel,
1398     &mst_e_mclk_sel,
1399     &mst_f_mclk_sel,
1400     &mst_a_mclk_div,
1401     &mst_b_mclk_div,
1402     &mst_c_mclk_div,
1403     &mst_d_mclk_div,
1404     &mst_e_mclk_div,
1405     &mst_f_mclk_div,
1406     &mst_a_mclk,
1407     &mst_b_mclk,
1408     &mst_c_mclk,
1409     &mst_d_mclk,
1410     &mst_e_mclk,
1411     &mst_f_mclk,
1412     &spdifout_clk_sel,
1413     &spdifout_clk_div,
1414     &spdifout_clk,
1415     &spdifin_clk_sel,
1416     &spdifin_clk_div,
1417     &spdifin_clk,
1418     &pdm_dclk_sel,
1419     &pdm_dclk_div,
1420     &pdm_dclk,
1421     &pdm_sysclk_sel,
1422     &pdm_sysclk_div,
1423     &pdm_sysclk,
1424     &mst_a_sclk_pre_en,
1425     &mst_b_sclk_pre_en,
1426     &mst_c_sclk_pre_en,
1427     &mst_d_sclk_pre_en,
1428     &mst_e_sclk_pre_en,
1429     &mst_f_sclk_pre_en,
1430     &mst_a_sclk_div,
1431     &mst_b_sclk_div,
1432     &mst_c_sclk_div,
1433     &mst_d_sclk_div,
1434     &mst_e_sclk_div,
1435     &mst_f_sclk_div,
1436     &mst_a_sclk_post_en,
1437     &mst_b_sclk_post_en,
1438     &mst_c_sclk_post_en,
1439     &mst_d_sclk_post_en,
1440     &mst_e_sclk_post_en,
1441     &mst_f_sclk_post_en,
1442     &mst_a_sclk,
1443     &mst_b_sclk,
1444     &mst_c_sclk,
1445     &mst_d_sclk,
1446     &mst_e_sclk,
1447     &mst_f_sclk,
1448     &mst_a_lrclk_div,
1449     &mst_b_lrclk_div,
1450     &mst_c_lrclk_div,
1451     &mst_d_lrclk_div,
1452     &mst_e_lrclk_div,
1453     &mst_f_lrclk_div,
1454     &mst_a_lrclk,
1455     &mst_b_lrclk,
1456     &mst_c_lrclk,
1457     &mst_d_lrclk,
1458     &mst_e_lrclk,
1459     &mst_f_lrclk,
1460     &tdmin_a_sclk_sel,
1461     &tdmin_b_sclk_sel,
1462     &tdmin_c_sclk_sel,
1463     &tdmin_lb_sclk_sel,
1464     &tdmout_a_sclk_sel,
1465     &tdmout_b_sclk_sel,
1466     &tdmout_c_sclk_sel,
1467     &tdmin_a_sclk_pre_en,
1468     &tdmin_b_sclk_pre_en,
1469     &tdmin_c_sclk_pre_en,
1470     &tdmin_lb_sclk_pre_en,
1471     &tdmout_a_sclk_pre_en,
1472     &tdmout_b_sclk_pre_en,
1473     &tdmout_c_sclk_pre_en,
1474     &tdmin_a_sclk_post_en,
1475     &tdmin_b_sclk_post_en,
1476     &tdmin_c_sclk_post_en,
1477     &tdmin_lb_sclk_post_en,
1478     &tdmout_a_sclk_post_en,
1479     &tdmout_b_sclk_post_en,
1480     &tdmout_c_sclk_post_en,
1481     &tdmin_a_sclk,
1482     &tdmin_b_sclk,
1483     &tdmin_c_sclk,
1484     &tdmin_lb_sclk,
1485     &g12a_tdmout_a_sclk,
1486     &g12a_tdmout_b_sclk,
1487     &g12a_tdmout_c_sclk,
1488     &tdmin_a_lrclk,
1489     &tdmin_b_lrclk,
1490     &tdmin_c_lrclk,
1491     &tdmin_lb_lrclk,
1492     &tdmout_a_lrclk,
1493     &tdmout_b_lrclk,
1494     &tdmout_c_lrclk,
1495     &spdifout_b_clk_sel,
1496     &spdifout_b_clk_div,
1497     &spdifout_b_clk,
1498     &g12a_tdm_mclk_pad_0,
1499     &g12a_tdm_mclk_pad_1,
1500     &g12a_tdm_lrclk_pad_0,
1501     &g12a_tdm_lrclk_pad_1,
1502     &g12a_tdm_lrclk_pad_2,
1503     &g12a_tdm_sclk_pad_0,
1504     &g12a_tdm_sclk_pad_1,
1505     &g12a_tdm_sclk_pad_2,
1506     &toram,
1507     &eqdrc,
1508 };
1509
1510 static struct clk_regmap *const sm1_clk_regmaps[] = {
1511     &ddr_arb,
1512     &pdm,
1513     &tdmin_a,
1514     &tdmin_b,
1515     &tdmin_c,
1516     &tdmin_lb,
1517     &tdmout_a,
1518     &tdmout_b,
1519     &tdmout_c,
1520     &frddr_a,
1521     &frddr_b,
1522     &frddr_c,
1523     &toddr_a,
1524     &toddr_b,
1525     &toddr_c,
1526     &loopback,
1527     &spdifin,
1528     &spdifout,
1529     &resample,
1530     &spdifout_b,
1531     &sm1_mst_a_mclk_sel,
1532     &sm1_mst_b_mclk_sel,
1533     &sm1_mst_c_mclk_sel,
1534     &sm1_mst_d_mclk_sel,
1535     &sm1_mst_e_mclk_sel,
1536     &sm1_mst_f_mclk_sel,
1537     &sm1_mst_a_mclk_div,
1538     &sm1_mst_b_mclk_div,
1539     &sm1_mst_c_mclk_div,
1540     &sm1_mst_d_mclk_div,
1541     &sm1_mst_e_mclk_div,
1542     &sm1_mst_f_mclk_div,
1543     &sm1_mst_a_mclk,
1544     &sm1_mst_b_mclk,
1545     &sm1_mst_c_mclk,
1546     &sm1_mst_d_mclk,
1547     &sm1_mst_e_mclk,
1548     &sm1_mst_f_mclk,
1549     &spdifout_clk_sel,
1550     &spdifout_clk_div,
1551     &spdifout_clk,
1552     &spdifin_clk_sel,
1553     &spdifin_clk_div,
1554     &spdifin_clk,
1555     &pdm_dclk_sel,
1556     &pdm_dclk_div,
1557     &pdm_dclk,
1558     &pdm_sysclk_sel,
1559     &pdm_sysclk_div,
1560     &pdm_sysclk,
1561     &mst_a_sclk_pre_en,
1562     &mst_b_sclk_pre_en,
1563     &mst_c_sclk_pre_en,
1564     &mst_d_sclk_pre_en,
1565     &mst_e_sclk_pre_en,
1566     &mst_f_sclk_pre_en,
1567     &mst_a_sclk_div,
1568     &mst_b_sclk_div,
1569     &mst_c_sclk_div,
1570     &mst_d_sclk_div,
1571     &mst_e_sclk_div,
1572     &mst_f_sclk_div,
1573     &mst_a_sclk_post_en,
1574     &mst_b_sclk_post_en,
1575     &mst_c_sclk_post_en,
1576     &mst_d_sclk_post_en,
1577     &mst_e_sclk_post_en,
1578     &mst_f_sclk_post_en,
1579     &mst_a_sclk,
1580     &mst_b_sclk,
1581     &mst_c_sclk,
1582     &mst_d_sclk,
1583     &mst_e_sclk,
1584     &mst_f_sclk,
1585     &mst_a_lrclk_div,
1586     &mst_b_lrclk_div,
1587     &mst_c_lrclk_div,
1588     &mst_d_lrclk_div,
1589     &mst_e_lrclk_div,
1590     &mst_f_lrclk_div,
1591     &mst_a_lrclk,
1592     &mst_b_lrclk,
1593     &mst_c_lrclk,
1594     &mst_d_lrclk,
1595     &mst_e_lrclk,
1596     &mst_f_lrclk,
1597     &tdmin_a_sclk_sel,
1598     &tdmin_b_sclk_sel,
1599     &tdmin_c_sclk_sel,
1600     &tdmin_lb_sclk_sel,
1601     &tdmout_a_sclk_sel,
1602     &tdmout_b_sclk_sel,
1603     &tdmout_c_sclk_sel,
1604     &tdmin_a_sclk_pre_en,
1605     &tdmin_b_sclk_pre_en,
1606     &tdmin_c_sclk_pre_en,
1607     &tdmin_lb_sclk_pre_en,
1608     &tdmout_a_sclk_pre_en,
1609     &tdmout_b_sclk_pre_en,
1610     &tdmout_c_sclk_pre_en,
1611     &tdmin_a_sclk_post_en,
1612     &tdmin_b_sclk_post_en,
1613     &tdmin_c_sclk_post_en,
1614     &tdmin_lb_sclk_post_en,
1615     &tdmout_a_sclk_post_en,
1616     &tdmout_b_sclk_post_en,
1617     &tdmout_c_sclk_post_en,
1618     &tdmin_a_sclk,
1619     &tdmin_b_sclk,
1620     &tdmin_c_sclk,
1621     &tdmin_lb_sclk,
1622     &g12a_tdmout_a_sclk,
1623     &g12a_tdmout_b_sclk,
1624     &g12a_tdmout_c_sclk,
1625     &tdmin_a_lrclk,
1626     &tdmin_b_lrclk,
1627     &tdmin_c_lrclk,
1628     &tdmin_lb_lrclk,
1629     &tdmout_a_lrclk,
1630     &tdmout_b_lrclk,
1631     &tdmout_c_lrclk,
1632     &spdifout_b_clk_sel,
1633     &spdifout_b_clk_div,
1634     &spdifout_b_clk,
1635     &sm1_tdm_mclk_pad_0,
1636     &sm1_tdm_mclk_pad_1,
1637     &sm1_tdm_lrclk_pad_0,
1638     &sm1_tdm_lrclk_pad_1,
1639     &sm1_tdm_lrclk_pad_2,
1640     &sm1_tdm_sclk_pad_0,
1641     &sm1_tdm_sclk_pad_1,
1642     &sm1_tdm_sclk_pad_2,
1643     &sm1_aud_top,
1644     &toram,
1645     &eqdrc,
1646     &resample_b,
1647     &tovad,
1648     &locker,
1649     &spdifin_lb,
1650     &frddr_d,
1651     &toddr_d,
1652     &loopback_b,
1653     &sm1_clk81_en,
1654     &sm1_sysclk_a_div,
1655     &sm1_sysclk_a_en,
1656     &sm1_sysclk_b_div,
1657     &sm1_sysclk_b_en,
1658 };
1659
1660 struct axg_audio_reset_data {
1661     struct reset_controller_dev rstc;
1662     struct regmap *map;
1663     unsigned int offset;
1664 };
1665
1666 static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
1667                     unsigned long id,
1668                     unsigned int *reg,
1669                     unsigned int *bit)
1670 {
1671     unsigned int stride = regmap_get_reg_stride(rst->map);
1672
1673     *reg = (id / (stride * BITS_PER_BYTE)) * stride;
1674     *reg += rst->offset;
1675     *bit = id % (stride * BITS_PER_BYTE);
1676 }
1677
1678 static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
1679                 unsigned long id, bool assert)
1680 {
1681     struct axg_audio_reset_data *rst =
1682         container_of(rcdev, struct axg_audio_reset_data, rstc);
1683     unsigned int offset, bit;
1684
1685     axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1686
1687     regmap_update_bits(rst->map, offset, BIT(bit),
1688             assert ? BIT(bit) : 0);
1689
1690     return 0;
1691 }
1692
1693 static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
1694                 unsigned long id)
1695 {
1696     struct axg_audio_reset_data *rst =
1697         container_of(rcdev, struct axg_audio_reset_data, rstc);
1698     unsigned int val, offset, bit;
1699
1700     axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1701
1702     regmap_read(rst->map, offset, &val);
1703
1704     return !!(val & BIT(bit));
1705 }
1706
1707 static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
1708                 unsigned long id)
1709 {
1710     return axg_audio_reset_update(rcdev, id, true);
1711 }
1712
1713 static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
1714                 unsigned long id)
1715 {
1716     return axg_audio_reset_update(rcdev, id, false);
1717 }
1718
1719 static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
1720                 unsigned long id)
1721 {
1722     int ret;
1723
1724     ret = axg_audio_reset_assert(rcdev, id);
1725     if (ret)
1726         return ret;
1727
1728     return axg_audio_reset_deassert(rcdev, id);
1729 }
1730
1731 static const struct reset_control_ops axg_audio_rstc_ops = {
1732     .assert = axg_audio_reset_assert,
1733     .deassert = axg_audio_reset_deassert,
1734     .reset = axg_audio_reset_toggle,
1735     .status = axg_audio_reset_status,
1736 };
1737
1738 static const struct regmap_config axg_audio_regmap_cfg = {
1739     .reg_bits   = 32,
1740     .val_bits   = 32,
1741     .reg_stride = 4,
1742     .max_register   = AUDIO_CLK_SPDIFOUT_B_CTRL,
1743 };
1744
1745 struct audioclk_data {
1746     struct clk_regmap *const *regmap_clks;
1747     unsigned int regmap_clk_num;
1748     struct clk_hw_onecell_data *hw_onecell_data;
1749     unsigned int reset_offset;
1750     unsigned int reset_num;
1751 };
1752
1753 static int axg_audio_clkc_probe(struct platform_device *pdev)
1754 {
1755     struct device *dev = &pdev->dev;
1756     const struct audioclk_data *data;
1757     struct axg_audio_reset_data *rst;
1758     struct regmap *map;
1759     void __iomem *regs;
1760     struct clk_hw *hw;
1761     struct clk *clk;
1762     int ret, i;
1763
1764     data = of_device_get_match_data(dev);
1765     if (!data)
1766         return -EINVAL;
1767
1768     regs = devm_platform_ioremap_resource(pdev, 0);
1769     if (IS_ERR(regs))
1770         return PTR_ERR(regs);
1771
1772     map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
1773     if (IS_ERR(map)) {
1774         dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
1775         return PTR_ERR(map);
1776     }
1777
1778     /* Get the mandatory peripheral clock */
1779     clk = devm_clk_get_enabled(dev, "pclk");
1780     if (IS_ERR(clk))
1781         return PTR_ERR(clk);
1782
1783     ret = device_reset(dev);
1784     if (ret) {
1785         dev_err_probe(dev, ret, "failed to reset device\n");
1786         return ret;
1787     }
1788
1789     /* Populate regmap for the regmap backed clocks */
1790     for (i = 0; i < data->regmap_clk_num; i++)
1791         data->regmap_clks[i]->map = map;
1792
1793     /* Take care to skip the registered input clocks */
1794     for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
1795         const char *name;
1796
1797         hw = data->hw_onecell_data->hws[i];
1798         /* array might be sparse */
1799         if (!hw)
1800             continue;
1801
1802         name = hw->init->name;
1803
1804         ret = devm_clk_hw_register(dev, hw);
1805         if (ret) {
1806             dev_err(dev, "failed to register clock %s\n", name);
1807             return ret;
1808         }
1809     }
1810
1811     ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1812                     data->hw_onecell_data);
1813     if (ret)
1814         return ret;
1815
1816     /* Stop here if there is no reset */
1817     if (!data->reset_num)
1818         return 0;
1819
1820     rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1821     if (!rst)
1822         return -ENOMEM;
1823
1824     rst->map = map;
1825     rst->offset = data->reset_offset;
1826     rst->rstc.nr_resets = data->reset_num;
1827     rst->rstc.ops = &axg_audio_rstc_ops;
1828     rst->rstc.of_node = dev->of_node;
1829     rst->rstc.owner = THIS_MODULE;
1830
1831     return devm_reset_controller_register(dev, &rst->rstc);
1832 }
1833
1834 static const struct audioclk_data axg_audioclk_data = {
1835     .regmap_clks = axg_clk_regmaps,
1836     .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1837     .hw_onecell_data = &axg_audio_hw_onecell_data,
1838 };
1839
1840 static const struct audioclk_data g12a_audioclk_data = {
1841     .regmap_clks = g12a_clk_regmaps,
1842     .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
1843     .hw_onecell_data = &g12a_audio_hw_onecell_data,
1844     .reset_offset = AUDIO_SW_RESET,
1845     .reset_num = 26,
1846 };
1847
1848 static const struct audioclk_data sm1_audioclk_data = {
1849     .regmap_clks = sm1_clk_regmaps,
1850     .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
1851     .hw_onecell_data = &sm1_audio_hw_onecell_data,
1852     .reset_offset = AUDIO_SM1_SW_RESET0,
1853     .reset_num = 39,
1854 };
1855
1856 static const struct of_device_id clkc_match_table[] = {
1857     {
1858         .compatible = "amlogic,axg-audio-clkc",
1859         .data = &axg_audioclk_data
1860     }, {
1861         .compatible = "amlogic,g12a-audio-clkc",
1862         .data = &g12a_audioclk_data
1863     }, {
1864         .compatible = "amlogic,sm1-audio-clkc",
1865         .data = &sm1_audioclk_data
1866     }, {}
1867 };
1868 MODULE_DEVICE_TABLE(of, clkc_match_table);
1869
1870 static struct platform_driver axg_audio_driver = {
1871     .probe      = axg_audio_clkc_probe,
1872     .driver     = {
1873         .name   = "axg-audio-clkc",
1874         .of_match_table = clkc_match_table,
1875     },
1876 };
1877 module_platform_driver(axg_audio_driver);
1878
1879 MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
1880 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
1881 MODULE_LICENSE("GPL v2");