OSCL-LXR |
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| Name | Size | Date (UTC) | Last indexed | Description | |
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| Name | Size | Date (UTC) | Last indexed | Description | |
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Parent directory | - | 2025-03-06 09:18:32 | ||
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axg-aoclk.c | 8357 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:51 | |
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axg-aoclk.h | 413 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:51 | |
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axg-audio.c | 63243 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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axg-audio.h | 4907 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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axg.c | 53806 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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axg.h | 4938 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-cpu-dyndiv.c | 2228 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-cpu-dyndiv.h | 422 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-dualdiv.c | 4173 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | The AO Domain embeds a dual/divider to generate a more precise 32,768KHz clock for low-power suspend mode and CEC. |
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clk-dualdiv.h | 683 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-mpll.c | 4181 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | MultiPhase Locked Loops are outputs from a PLL with additional frequency scaling capabilities. MPLL rates are calculated as: f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384) |
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clk-mpll.h | 712 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-phase.c | 5315 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-phase.h | 638 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-pll.c | 11374 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-pll.h | 993 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-regmap.c | 5103 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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clk-regmap.h | 3694 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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g12a-aoclk.c | 12134 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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g12a-aoclk.h | 896 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:52 | |
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g12a.c | 147598 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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g12a.h | 9020 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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gxbb-aoclk.c | 7353 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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gxbb-aoclk.h | 321 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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gxbb.c | 94090 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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gxbb.h | 8612 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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Kconfig | 3127 bytes | 2025-03-06 09:18:32 | - | |
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Makefile | 908 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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meson-aoclk.c | 2354 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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meson-aoclk.h | 907 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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meson-eeclk.c | 1457 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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meson-eeclk.h | 560 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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meson8-ddr.c | 3409 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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meson8b.c | 111411 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:53 | |
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meson8b.h | 7645 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:54 | |
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parm.h | 1109 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:54 | |
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sclk-div.c | 6080 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:54 | |
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sclk-div.h | 443 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:54 | |
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vid-pll-div.c | 2902 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:54 | |
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vid-pll-div.h | 406 bytes | 2025-03-06 09:18:32 | 2025-03-06 11:57:54 |
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