clk/mediatek/reset.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 MediaTek Inc.
0004  */
0005
0006 #ifndef __DRV_CLK_MTK_RESET_H
0007 #define __DRV_CLK_MTK_RESET_H
0008
0009 #include <linux/reset-controller.h>
0010 #include <linux/types.h>
0011
0012 #define RST_NR_PER_BANK 32
0013
0014 /* Infra global controller reset set register */
0015 #define INFRA_RST0_SET_OFFSET 0x120
0016 #define INFRA_RST1_SET_OFFSET 0x130
0017 #define INFRA_RST2_SET_OFFSET 0x140
0018 #define INFRA_RST3_SET_OFFSET 0x150
0019 #define INFRA_RST4_SET_OFFSET 0x730
0020
0021 /**
0022  * enum mtk_reset_version - Version of MediaTek clock reset controller.
0023  * @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
0024  * @MTK_RST_SET_CLR: Use separate registers for bit set and clear.
0025  * @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
0026  */
0027 enum mtk_reset_version {
0028     MTK_RST_SIMPLE = 0,
0029     MTK_RST_SET_CLR,
0030     MTK_RST_MAX,
0031 };
0032
0033 /**
0034  * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
0035  * @version: Reset version which is defined in enum mtk_reset_version.
0036  * @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
0037  * @rst_bank_nr: Quantity of reset bank.
0038  * @rst_idx_map:Pointer to an array containing ids if input argument is index.
0039  *      This array is not necessary if our input argument does not mean index.
0040  * @rst_idx_map_nr: Quantity of reset index map.
0041  */
0042 struct mtk_clk_rst_desc {
0043     enum mtk_reset_version version;
0044     u16 *rst_bank_ofs;
0045     u32 rst_bank_nr;
0046     u16 *rst_idx_map;
0047     u32 rst_idx_map_nr;
0048 };
0049
0050 /**
0051  * struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
0052  * @regmap: Pointer to base address of reset register address.
0053  * @rcdev: Reset controller device.
0054  * @desc: Pointer to description of the reset controller.
0055  */
0056 struct mtk_clk_rst_data {
0057     struct regmap *regmap;
0058     struct reset_controller_dev rcdev;
0059     const struct mtk_clk_rst_desc *desc;
0060 };
0061
0062 /**
0063  * mtk_register_reset_controller - Register MediaTek clock reset controller
0064  * @np: Pointer to device node.
0065  * @desc: Constant pointer to description of clock reset.
0066  *
0067  * Return: 0 on success and errorno otherwise.
0068  */
0069 int mtk_register_reset_controller(struct device_node *np,
0070                   const struct mtk_clk_rst_desc *desc);
0071
0072 /**
0073  * mtk_register_reset_controller - Register mediatek clock reset controller with device
0074  * @np: Pointer to device.
0075  * @desc: Constant pointer to description of clock reset.
0076  *
0077  * Return: 0 on success and errorno otherwise.
0078  */
0079 int mtk_register_reset_controller_with_dev(struct device *dev,
0080                        const struct mtk_clk_rst_desc *desc);
0081
0082 #endif /* __DRV_CLK_MTK_RESET_H */