clk/mediatek/reset.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  */
0005
0006 #include <linux/mfd/syscon.h>
0007 #include <linux/module.h>
0008 #include <linux/of.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/regmap.h>
0011 #include <linux/slab.h>
0012
0013 #include "reset.h"
0014
0015 static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
0016 {
0017     return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
0018 }
0019
0020 static int mtk_reset_update(struct reset_controller_dev *rcdev,
0021                 unsigned long id, bool deassert)
0022 {
0023     struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
0024     unsigned int val = deassert ? 0 : ~0;
0025
0026     return regmap_update_bits(data->regmap,
0027                   data->desc->rst_bank_ofs[id / RST_NR_PER_BANK],
0028                   BIT(id % RST_NR_PER_BANK), val);
0029 }
0030
0031 static int mtk_reset_assert(struct reset_controller_dev *rcdev,
0032                 unsigned long id)
0033 {
0034     return mtk_reset_update(rcdev, id, false);
0035 }
0036
0037 static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
0038                   unsigned long id)
0039 {
0040     return mtk_reset_update(rcdev, id, true);
0041 }
0042
0043 static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
0044 {
0045     int ret;
0046
0047     ret = mtk_reset_assert(rcdev, id);
0048     if (ret)
0049         return ret;
0050
0051     return mtk_reset_deassert(rcdev, id);
0052 }
0053
0054 static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
0055                     unsigned long id, bool deassert)
0056 {
0057     struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
0058     unsigned int deassert_ofs = deassert ? 0x4 : 0;
0059
0060     return regmap_write(data->regmap,
0061                 data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] +
0062                 deassert_ofs,
0063                 BIT(id % RST_NR_PER_BANK));
0064 }
0065
0066 static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
0067                     unsigned long id)
0068 {
0069     return mtk_reset_update_set_clr(rcdev, id, false);
0070 }
0071
0072 static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
0073                       unsigned long id)
0074 {
0075     return mtk_reset_update_set_clr(rcdev, id, true);
0076 }
0077
0078 static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
0079                  unsigned long id)
0080 {
0081     int ret;
0082
0083     ret = mtk_reset_assert_set_clr(rcdev, id);
0084     if (ret)
0085         return ret;
0086     return mtk_reset_deassert_set_clr(rcdev, id);
0087 }
0088
0089 static const struct reset_control_ops mtk_reset_ops = {
0090     .assert = mtk_reset_assert,
0091     .deassert = mtk_reset_deassert,
0092     .reset = mtk_reset,
0093 };
0094
0095 static const struct reset_control_ops mtk_reset_ops_set_clr = {
0096     .assert = mtk_reset_assert_set_clr,
0097     .deassert = mtk_reset_deassert_set_clr,
0098     .reset = mtk_reset_set_clr,
0099 };
0100
0101 static int reset_xlate(struct reset_controller_dev *rcdev,
0102                const struct of_phandle_args *reset_spec)
0103 {
0104     struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
0105
0106     if (reset_spec->args[0] >= rcdev->nr_resets ||
0107         reset_spec->args[0] >= data->desc->rst_idx_map_nr)
0108         return -EINVAL;
0109
0110     return data->desc->rst_idx_map[reset_spec->args[0]];
0111 }
0112
0113 int mtk_register_reset_controller(struct device_node *np,
0114                   const struct mtk_clk_rst_desc *desc)
0115 {
0116     struct regmap *regmap;
0117     const struct reset_control_ops *rcops = NULL;
0118     struct mtk_clk_rst_data *data;
0119     int ret;
0120
0121     if (!desc) {
0122         pr_err("mtk clock reset desc is NULL\n");
0123         return -EINVAL;
0124     }
0125
0126     switch (desc->version) {
0127     case MTK_RST_SIMPLE:
0128         rcops = &mtk_reset_ops;
0129         break;
0130     case MTK_RST_SET_CLR:
0131         rcops = &mtk_reset_ops_set_clr;
0132         break;
0133     default:
0134         pr_err("Unknown reset version %d\n", desc->version);
0135         return -EINVAL;
0136     }
0137
0138     regmap = device_node_to_regmap(np);
0139     if (IS_ERR(regmap)) {
0140         pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
0141         return -EINVAL;
0142     }
0143
0144     data = kzalloc(sizeof(*data), GFP_KERNEL);
0145     if (!data)
0146         return -ENOMEM;
0147
0148     data->desc = desc;
0149     data->regmap = regmap;
0150     data->rcdev.owner = THIS_MODULE;
0151     data->rcdev.ops = rcops;
0152     data->rcdev.of_node = np;
0153
0154     if (data->desc->rst_idx_map_nr > 0) {
0155         data->rcdev.of_reset_n_cells = 1;
0156         data->rcdev.nr_resets = desc->rst_idx_map_nr;
0157         data->rcdev.of_xlate = reset_xlate;
0158     } else {
0159         data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
0160     }
0161
0162     ret = reset_controller_register(&data->rcdev);
0163     if (ret) {
0164         pr_err("could not register reset controller: %d\n", ret);
0165         kfree(data);
0166         return ret;
0167     }
0168
0169     return 0;
0170 }
0171
0172 int mtk_register_reset_controller_with_dev(struct device *dev,
0173                        const struct mtk_clk_rst_desc *desc)
0174 {
0175     struct device_node *np = dev->of_node;
0176     struct regmap *regmap;
0177     const struct reset_control_ops *rcops = NULL;
0178     struct mtk_clk_rst_data *data;
0179     int ret;
0180
0181     if (!desc) {
0182         dev_err(dev, "mtk clock reset desc is NULL\n");
0183         return -EINVAL;
0184     }
0185
0186     switch (desc->version) {
0187     case MTK_RST_SIMPLE:
0188         rcops = &mtk_reset_ops;
0189         break;
0190     case MTK_RST_SET_CLR:
0191         rcops = &mtk_reset_ops_set_clr;
0192         break;
0193     default:
0194         dev_err(dev, "Unknown reset version %d\n", desc->version);
0195         return -EINVAL;
0196     }
0197
0198     regmap = device_node_to_regmap(np);
0199     if (IS_ERR(regmap)) {
0200         dev_err(dev, "Cannot find regmap %pe\n", regmap);
0201         return -EINVAL;
0202     }
0203
0204     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0205     if (!data)
0206         return -ENOMEM;
0207
0208     data->desc = desc;
0209     data->regmap = regmap;
0210     data->rcdev.owner = THIS_MODULE;
0211     data->rcdev.ops = rcops;
0212     data->rcdev.of_node = np;
0213     data->rcdev.dev = dev;
0214
0215     if (data->desc->rst_idx_map_nr > 0) {
0216         data->rcdev.of_reset_n_cells = 1;
0217         data->rcdev.nr_resets = desc->rst_idx_map_nr;
0218         data->rcdev.of_xlate = reset_xlate;
0219     } else {
0220         data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
0221     }
0222
0223     ret = devm_reset_controller_register(dev, &data->rcdev);
0224     if (ret) {
0225         dev_err(dev, "could not register reset controller: %d\n", ret);
0226         return ret;
0227     }
0228
0229     return 0;
0230 }
0231
0232 MODULE_LICENSE("GPL");