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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: James Liao <jamesjj.liao@mediatek.com>
0005  */
0006 
0007 #include <linux/clk-provider.h>
0008 #include <linux/container_of.h>
0009 #include <linux/delay.h>
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of_address.h>
0014 #include <linux/slab.h>
0015 
0016 #include "clk-pll.h"
0017 
0018 #define MHZ         (1000 * 1000)
0019 
0020 #define REG_CON0        0
0021 #define REG_CON1        4
0022 
0023 #define CON0_BASE_EN        BIT(0)
0024 #define CON0_PWR_ON     BIT(0)
0025 #define CON0_ISO_EN     BIT(1)
0026 #define PCW_CHG_MASK        BIT(31)
0027 
0028 #define AUDPLL_TUNER_EN     BIT(31)
0029 
0030 #define POSTDIV_MASK        0x7
0031 
0032 /* default 7 bits integer, can be overridden with pcwibits. */
0033 #define INTEGER_BITS        7
0034 
0035 /*
0036  * MediaTek PLLs are configured through their pcw value. The pcw value describes
0037  * a divider in the PLL feedback loop which consists of 7 bits for the integer
0038  * part and the remaining bits (if present) for the fractional part. Also they
0039  * have a 3 bit power-of-two post divider.
0040  */
0041 
0042 struct mtk_clk_pll {
0043     struct clk_hw   hw;
0044     void __iomem    *base_addr;
0045     void __iomem    *pd_addr;
0046     void __iomem    *pwr_addr;
0047     void __iomem    *tuner_addr;
0048     void __iomem    *tuner_en_addr;
0049     void __iomem    *pcw_addr;
0050     void __iomem    *pcw_chg_addr;
0051     void __iomem    *en_addr;
0052     const struct mtk_pll_data *data;
0053 };
0054 
0055 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
0056 {
0057     return container_of(hw, struct mtk_clk_pll, hw);
0058 }
0059 
0060 static int mtk_pll_is_prepared(struct clk_hw *hw)
0061 {
0062     struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
0063 
0064     return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
0065 }
0066 
0067 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
0068         u32 pcw, int postdiv)
0069 {
0070     int pcwbits = pll->data->pcwbits;
0071     int pcwfbits = 0;
0072     int ibits;
0073     u64 vco;
0074     u8 c = 0;
0075 
0076     /* The fractional part of the PLL divider. */
0077     ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
0078     if (pcwbits > ibits)
0079         pcwfbits = pcwbits - ibits;
0080 
0081     vco = (u64)fin * pcw;
0082 
0083     if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
0084         c = 1;
0085 
0086     vco >>= pcwfbits;
0087 
0088     if (c)
0089         vco++;
0090 
0091     return ((unsigned long)vco + postdiv - 1) / postdiv;
0092 }
0093 
0094 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
0095 {
0096     u32 r;
0097 
0098     if (pll->tuner_en_addr) {
0099         r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
0100         writel(r, pll->tuner_en_addr);
0101     } else if (pll->tuner_addr) {
0102         r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
0103         writel(r, pll->tuner_addr);
0104     }
0105 }
0106 
0107 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
0108 {
0109     u32 r;
0110 
0111     if (pll->tuner_en_addr) {
0112         r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
0113         writel(r, pll->tuner_en_addr);
0114     } else if (pll->tuner_addr) {
0115         r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
0116         writel(r, pll->tuner_addr);
0117     }
0118 }
0119 
0120 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
0121         int postdiv)
0122 {
0123     u32 chg, val;
0124 
0125     /* disable tuner */
0126     __mtk_pll_tuner_disable(pll);
0127 
0128     /* set postdiv */
0129     val = readl(pll->pd_addr);
0130     val &= ~(POSTDIV_MASK << pll->data->pd_shift);
0131     val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
0132 
0133     /* postdiv and pcw need to set at the same time if on same register */
0134     if (pll->pd_addr != pll->pcw_addr) {
0135         writel(val, pll->pd_addr);
0136         val = readl(pll->pcw_addr);
0137     }
0138 
0139     /* set pcw */
0140     val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
0141             pll->data->pcw_shift);
0142     val |= pcw << pll->data->pcw_shift;
0143     writel(val, pll->pcw_addr);
0144     chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
0145     writel(chg, pll->pcw_chg_addr);
0146     if (pll->tuner_addr)
0147         writel(val + 1, pll->tuner_addr);
0148 
0149     /* restore tuner_en */
0150     __mtk_pll_tuner_enable(pll);
0151 
0152     udelay(20);
0153 }
0154 
0155 /*
0156  * mtk_pll_calc_values - calculate good values for a given input frequency.
0157  * @pll:    The pll
0158  * @pcw:    The pcw value (output)
0159  * @postdiv:    The post divider (output)
0160  * @freq:   The desired target frequency
0161  * @fin:    The input frequency
0162  *
0163  */
0164 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
0165         u32 freq, u32 fin)
0166 {
0167     unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
0168     const struct mtk_pll_div_table *div_table = pll->data->div_table;
0169     u64 _pcw;
0170     int ibits;
0171     u32 val;
0172 
0173     if (freq > pll->data->fmax)
0174         freq = pll->data->fmax;
0175 
0176     if (div_table) {
0177         if (freq > div_table[0].freq)
0178             freq = div_table[0].freq;
0179 
0180         for (val = 0; div_table[val + 1].freq != 0; val++) {
0181             if (freq > div_table[val + 1].freq)
0182                 break;
0183         }
0184         *postdiv = 1 << val;
0185     } else {
0186         for (val = 0; val < 5; val++) {
0187             *postdiv = 1 << val;
0188             if ((u64)freq * *postdiv >= fmin)
0189                 break;
0190         }
0191     }
0192 
0193     /* _pcw = freq * postdiv / fin * 2^pcwfbits */
0194     ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
0195     _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
0196     do_div(_pcw, fin);
0197 
0198     *pcw = (u32)_pcw;
0199 }
0200 
0201 static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0202         unsigned long parent_rate)
0203 {
0204     struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
0205     u32 pcw = 0;
0206     u32 postdiv;
0207 
0208     mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
0209     mtk_pll_set_rate_regs(pll, pcw, postdiv);
0210 
0211     return 0;
0212 }
0213 
0214 static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
0215         unsigned long parent_rate)
0216 {
0217     struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
0218     u32 postdiv;
0219     u32 pcw;
0220 
0221     postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
0222     postdiv = 1 << postdiv;
0223 
0224     pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
0225     pcw &= GENMASK(pll->data->pcwbits - 1, 0);
0226 
0227     return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
0228 }
0229 
0230 static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0231         unsigned long *prate)
0232 {
0233     struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
0234     u32 pcw = 0;
0235     int postdiv;
0236 
0237     mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
0238 
0239     return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
0240 }
0241 
0242 static int mtk_pll_prepare(struct clk_hw *hw)
0243 {
0244     struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
0245     u32 r;
0246 
0247     r = readl(pll->pwr_addr) | CON0_PWR_ON;
0248     writel(r, pll->pwr_addr);
0249     udelay(1);
0250 
0251     r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
0252     writel(r, pll->pwr_addr);
0253     udelay(1);
0254 
0255     r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
0256     writel(r, pll->en_addr);
0257 
0258     if (pll->data->en_mask) {
0259         r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
0260         writel(r, pll->base_addr + REG_CON0);
0261     }
0262 
0263     __mtk_pll_tuner_enable(pll);
0264 
0265     udelay(20);
0266 
0267     if (pll->data->flags & HAVE_RST_BAR) {
0268         r = readl(pll->base_addr + REG_CON0);
0269         r |= pll->data->rst_bar_mask;
0270         writel(r, pll->base_addr + REG_CON0);
0271     }
0272 
0273     return 0;
0274 }
0275 
0276 static void mtk_pll_unprepare(struct clk_hw *hw)
0277 {
0278     struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
0279     u32 r;
0280 
0281     if (pll->data->flags & HAVE_RST_BAR) {
0282         r = readl(pll->base_addr + REG_CON0);
0283         r &= ~pll->data->rst_bar_mask;
0284         writel(r, pll->base_addr + REG_CON0);
0285     }
0286 
0287     __mtk_pll_tuner_disable(pll);
0288 
0289     if (pll->data->en_mask) {
0290         r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
0291         writel(r, pll->base_addr + REG_CON0);
0292     }
0293 
0294     r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
0295     writel(r, pll->en_addr);
0296 
0297     r = readl(pll->pwr_addr) | CON0_ISO_EN;
0298     writel(r, pll->pwr_addr);
0299 
0300     r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
0301     writel(r, pll->pwr_addr);
0302 }
0303 
0304 static const struct clk_ops mtk_pll_ops = {
0305     .is_prepared    = mtk_pll_is_prepared,
0306     .prepare    = mtk_pll_prepare,
0307     .unprepare  = mtk_pll_unprepare,
0308     .recalc_rate    = mtk_pll_recalc_rate,
0309     .round_rate = mtk_pll_round_rate,
0310     .set_rate   = mtk_pll_set_rate,
0311 };
0312 
0313 static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
0314         void __iomem *base)
0315 {
0316     struct mtk_clk_pll *pll;
0317     struct clk_init_data init = {};
0318     int ret;
0319     const char *parent_name = "clk26m";
0320 
0321     pll = kzalloc(sizeof(*pll), GFP_KERNEL);
0322     if (!pll)
0323         return ERR_PTR(-ENOMEM);
0324 
0325     pll->base_addr = base + data->reg;
0326     pll->pwr_addr = base + data->pwr_reg;
0327     pll->pd_addr = base + data->pd_reg;
0328     pll->pcw_addr = base + data->pcw_reg;
0329     if (data->pcw_chg_reg)
0330         pll->pcw_chg_addr = base + data->pcw_chg_reg;
0331     else
0332         pll->pcw_chg_addr = pll->base_addr + REG_CON1;
0333     if (data->tuner_reg)
0334         pll->tuner_addr = base + data->tuner_reg;
0335     if (data->tuner_en_reg || data->tuner_en_bit)
0336         pll->tuner_en_addr = base + data->tuner_en_reg;
0337     if (data->en_reg)
0338         pll->en_addr = base + data->en_reg;
0339     else
0340         pll->en_addr = pll->base_addr + REG_CON0;
0341     pll->hw.init = &init;
0342     pll->data = data;
0343 
0344     init.name = data->name;
0345     init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
0346     init.ops = &mtk_pll_ops;
0347     if (data->parent_name)
0348         init.parent_names = &data->parent_name;
0349     else
0350         init.parent_names = &parent_name;
0351     init.num_parents = 1;
0352 
0353     ret = clk_hw_register(NULL, &pll->hw);
0354 
0355     if (ret) {
0356         kfree(pll);
0357         return ERR_PTR(ret);
0358     }
0359 
0360     return &pll->hw;
0361 }
0362 
0363 static void mtk_clk_unregister_pll(struct clk_hw *hw)
0364 {
0365     struct mtk_clk_pll *pll;
0366 
0367     if (!hw)
0368         return;
0369 
0370     pll = to_mtk_clk_pll(hw);
0371 
0372     clk_hw_unregister(hw);
0373     kfree(pll);
0374 }
0375 
0376 int mtk_clk_register_plls(struct device_node *node,
0377               const struct mtk_pll_data *plls, int num_plls,
0378               struct clk_hw_onecell_data *clk_data)
0379 {
0380     void __iomem *base;
0381     int i;
0382     struct clk_hw *hw;
0383 
0384     base = of_iomap(node, 0);
0385     if (!base) {
0386         pr_err("%s(): ioremap failed\n", __func__);
0387         return -EINVAL;
0388     }
0389 
0390     for (i = 0; i < num_plls; i++) {
0391         const struct mtk_pll_data *pll = &plls[i];
0392 
0393         if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
0394             pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
0395                 node, pll->id);
0396             continue;
0397         }
0398 
0399         hw = mtk_clk_register_pll(pll, base);
0400 
0401         if (IS_ERR(hw)) {
0402             pr_err("Failed to register clk %s: %pe\n", pll->name,
0403                    hw);
0404             goto err;
0405         }
0406 
0407         clk_data->hws[pll->id] = hw;
0408     }
0409 
0410     return 0;
0411 
0412 err:
0413     while (--i >= 0) {
0414         const struct mtk_pll_data *pll = &plls[i];
0415 
0416         mtk_clk_unregister_pll(clk_data->hws[pll->id]);
0417         clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
0418     }
0419 
0420     iounmap(base);
0421 
0422     return PTR_ERR(hw);
0423 }
0424 EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
0425 
0426 static __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
0427                       const struct mtk_pll_data *data)
0428 {
0429     struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
0430 
0431     return pll->base_addr - data->reg;
0432 }
0433 
0434 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
0435                  struct clk_hw_onecell_data *clk_data)
0436 {
0437     __iomem void *base = NULL;
0438     int i;
0439 
0440     if (!clk_data)
0441         return;
0442 
0443     for (i = num_plls; i > 0; i--) {
0444         const struct mtk_pll_data *pll = &plls[i - 1];
0445 
0446         if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
0447             continue;
0448 
0449         /*
0450          * This is quite ugly but unfortunately the clks don't have
0451          * any device tied to them, so there's no place to store the
0452          * pointer to the I/O region base address. We have to fetch
0453          * it from one of the registered clks.
0454          */
0455         base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);
0456 
0457         mtk_clk_unregister_pll(clk_data->hws[pll->id]);
0458         clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
0459     }
0460 
0461     iounmap(base);
0462 }
0463 EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls);
0464 
0465 MODULE_LICENSE("GPL");
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