clk/mediatek/clk-mux.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2018 MediaTek Inc.
0004  * Author: Owen Chen <owen.chen@mediatek.com>
0005  */
0006
0007 #ifndef __DRV_CLK_MTK_MUX_H
0008 #define __DRV_CLK_MTK_MUX_H
0009
0010 #include <linux/spinlock.h>
0011 #include <linux/types.h>
0012
0013 struct clk;
0014 struct clk_hw_onecell_data;
0015 struct clk_ops;
0016 struct device_node;
0017
0018 struct mtk_mux {
0019     int id;
0020     const char *name;
0021     const char * const *parent_names;
0022     unsigned int flags;
0023
0024     u32 mux_ofs;
0025     u32 set_ofs;
0026     u32 clr_ofs;
0027     u32 upd_ofs;
0028
0029     u8 mux_shift;
0030     u8 mux_width;
0031     u8 gate_shift;
0032     s8 upd_shift;
0033
0034     const struct clk_ops *ops;
0035     signed char num_parents;
0036 };
0037
0038 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,      \
0039             _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
0040             _gate, _upd_ofs, _upd, _flags, _ops) {      \
0041         .id = _id,                      \
0042         .name = _name,                      \
0043         .mux_ofs = _mux_ofs,                    \
0044         .set_ofs = _mux_set_ofs,                \
0045         .clr_ofs = _mux_clr_ofs,                \
0046         .upd_ofs = _upd_ofs,                    \
0047         .mux_shift = _shift,                    \
0048         .mux_width = _width,                    \
0049         .gate_shift = _gate,                    \
0050         .upd_shift = _upd,                  \
0051         .parent_names = _parents,               \
0052         .num_parents = ARRAY_SIZE(_parents),            \
0053         .flags = _flags,                    \
0054         .ops = &_ops,                       \
0055     }
0056
0057 extern const struct clk_ops mtk_mux_clr_set_upd_ops;
0058 extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
0059
0060 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,  \
0061             _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
0062             _gate, _upd_ofs, _upd, _flags)          \
0063         GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,  \
0064             _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
0065             _gate, _upd_ofs, _upd, _flags,          \
0066             mtk_mux_gate_clr_set_upd_ops)
0067
0068 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,        \
0069             _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
0070             _gate, _upd_ofs, _upd)              \
0071         MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents,    \
0072             _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift,   \
0073             _width, _gate, _upd_ofs, _upd,          \
0074             CLK_SET_RATE_PARENT)
0075
0076 #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,         \
0077             _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
0078             _upd_ofs, _upd)                 \
0079         GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,  \
0080             _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
0081             0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,     \
0082             mtk_mux_clr_set_upd_ops)
0083
0084 int mtk_clk_register_muxes(const struct mtk_mux *muxes,
0085                int num, struct device_node *node,
0086                spinlock_t *lock,
0087                struct clk_hw_onecell_data *clk_data);
0088
0089 void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num,
0090                   struct clk_hw_onecell_data *clk_data);
0091
0092 #endif /* __DRV_CLK_MTK_MUX_H */