clk/mediatek/clk-mt8195-vdo1.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include "clk-gate.h"
0007 #include "clk-mtk.h"
0008
0009 #include <dt-bindings/clock/mt8195-clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/platform_device.h>
0012
0013 static const struct mtk_gate_regs vdo1_0_cg_regs = {
0014     .set_ofs = 0x104,
0015     .clr_ofs = 0x108,
0016     .sta_ofs = 0x100,
0017 };
0018
0019 static const struct mtk_gate_regs vdo1_1_cg_regs = {
0020     .set_ofs = 0x124,
0021     .clr_ofs = 0x128,
0022     .sta_ofs = 0x120,
0023 };
0024
0025 static const struct mtk_gate_regs vdo1_2_cg_regs = {
0026     .set_ofs = 0x134,
0027     .clr_ofs = 0x138,
0028     .sta_ofs = 0x130,
0029 };
0030
0031 static const struct mtk_gate_regs vdo1_3_cg_regs = {
0032     .set_ofs = 0x144,
0033     .clr_ofs = 0x148,
0034     .sta_ofs = 0x140,
0035 };
0036
0037 #define GATE_VDO1_0(_id, _name, _parent, _shift)            \
0038     GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0039
0040 #define GATE_VDO1_1(_id, _name, _parent, _shift)            \
0041     GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0042
0043 #define GATE_VDO1_2(_id, _name, _parent, _shift)            \
0044     GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0045
0046 #define GATE_VDO1_3(_id, _name, _parent, _shift)            \
0047     GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0048
0049 static const struct mtk_gate vdo1_clks[] = {
0050     /* VDO1_0 */
0051     GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
0052     GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1),
0053     GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2),
0054     GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3),
0055     GATE_VDO1_0(CLK_VDO1_FAKE_ENG, "vdo1_fake_eng", "top_vpp", 4),
0056     GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5),
0057     GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6),
0058     GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7),
0059     GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8),
0060     GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9),
0061     GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10),
0062     GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11),
0063     GATE_VDO1_0(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 12),
0064     GATE_VDO1_0(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 13),
0065     GATE_VDO1_0(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 14),
0066     GATE_VDO1_0(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 15),
0067     GATE_VDO1_0(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 16),
0068     GATE_VDO1_0(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 17),
0069     GATE_VDO1_0(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 18),
0070     GATE_VDO1_0(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 19),
0071     GATE_VDO1_0(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 20),
0072     GATE_VDO1_0(CLK_VDO1_DP_INTF0_MM, "vdo1_dp_intf0_mm", "top_vpp", 21),
0073     GATE_VDO1_0(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm", "top_vpp", 22),
0074     GATE_VDO1_0(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm", "top_vpp", 23),
0075     GATE_VDO1_0(CLK_VDO1_DISP_MONITOR, "vdo1_disp_monitor", "top_vpp", 24),
0076     GATE_VDO1_0(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 25),
0077     GATE_VDO1_0(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 26),
0078     GATE_VDO1_0(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 27),
0079     GATE_VDO1_0(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 28),
0080     GATE_VDO1_0(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 29),
0081     GATE_VDO1_0(CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC, "vdo1_vdo0_dsc_to_vdo1_dl_async",
0082             "top_vpp", 30),
0083     GATE_VDO1_0(CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC, "vdo1_vdo0_merge_to_vdo1_dl_async",
0084             "top_vpp", 31),
0085     /* VDO1_1 */
0086     GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0),
0087     GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1),
0088     GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2),
0089     GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16),
0090     GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17),
0091     GATE_VDO1_1(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18),
0092     GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19),
0093     GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20),
0094     GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21),
0095     GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22),
0096     GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23),
0097     /* VDO1_2 */
0098     GATE_VDO1_2(CLK_VDO1_DPI0, "vdo1_dpi0", "top_vpp", 0),
0099     GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "top_vpp", 1),
0100     GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1", "top_vpp", 8),
0101     GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "top_vpp", 9),
0102     GATE_VDO1_2(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_vpp", 16),
0103     GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17),
0104     /* VDO1_3 */
0105     GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8),
0106 };
0107
0108 static int clk_mt8195_vdo1_probe(struct platform_device *pdev)
0109 {
0110     struct device *dev = &pdev->dev;
0111     struct device_node *node = dev->parent->of_node;
0112     struct clk_hw_onecell_data *clk_data;
0113     int r;
0114
0115     clk_data = mtk_alloc_clk_data(CLK_VDO1_NR_CLK);
0116     if (!clk_data)
0117         return -ENOMEM;
0118
0119     r = mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
0120     if (r)
0121         goto free_vdo1_data;
0122
0123     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0124     if (r)
0125         goto unregister_gates;
0126
0127     platform_set_drvdata(pdev, clk_data);
0128
0129     return r;
0130
0131 unregister_gates:
0132     mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
0133 free_vdo1_data:
0134     mtk_free_clk_data(clk_data);
0135     return r;
0136 }
0137
0138 static int clk_mt8195_vdo1_remove(struct platform_device *pdev)
0139 {
0140     struct device *dev = &pdev->dev;
0141     struct device_node *node = dev->parent->of_node;
0142     struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
0143
0144     of_clk_del_provider(node);
0145     mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
0146     mtk_free_clk_data(clk_data);
0147
0148     return 0;
0149 }
0150
0151 static struct platform_driver clk_mt8195_vdo1_drv = {
0152     .probe = clk_mt8195_vdo1_probe,
0153     .remove = clk_mt8195_vdo1_remove,
0154     .driver = {
0155         .name = "clk-mt8195-vdo1",
0156     },
0157 };
0158 builtin_platform_driver(clk_mt8195_vdo1_drv);