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0006 #include "clk-gate.h"
0007 #include "clk-mtk.h"
0008
0009 #include <dt-bindings/clock/mt8195-clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/platform_device.h>
0012
0013 static const struct mtk_gate_regs vdo0_0_cg_regs = {
0014 .set_ofs = 0x104,
0015 .clr_ofs = 0x108,
0016 .sta_ofs = 0x100,
0017 };
0018
0019 static const struct mtk_gate_regs vdo0_1_cg_regs = {
0020 .set_ofs = 0x114,
0021 .clr_ofs = 0x118,
0022 .sta_ofs = 0x110,
0023 };
0024
0025 static const struct mtk_gate_regs vdo0_2_cg_regs = {
0026 .set_ofs = 0x124,
0027 .clr_ofs = 0x128,
0028 .sta_ofs = 0x120,
0029 };
0030
0031 #define GATE_VDO0_0(_id, _name, _parent, _shift) \
0032 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0033
0034 #define GATE_VDO0_1(_id, _name, _parent, _shift) \
0035 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0036
0037 #define GATE_VDO0_2(_id, _name, _parent, _shift) \
0038 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0039
0040 static const struct mtk_gate vdo0_clks[] = {
0041
0042 GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
0043 GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 2),
0044 GATE_VDO0_0(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "top_vpp", 3),
0045 GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
0046 GATE_VDO0_0(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "top_vpp", 5),
0047 GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 6),
0048 GATE_VDO0_0(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "top_vpp", 7),
0049 GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
0050 GATE_VDO0_0(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "top_vpp", 9),
0051 GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
0052 GATE_VDO0_0(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "top_vpp", 11),
0053 GATE_VDO0_0(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "top_vpp", 16),
0054 GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
0055 GATE_VDO0_0(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "top_vpp", 18),
0056 GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
0057 GATE_VDO0_0(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "top_vpp", 20),
0058 GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
0059 GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
0060 GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
0061 GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
0062 GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
0063 GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 26),
0064 GATE_VDO0_0(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "top_vpp", 27),
0065 GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
0066 GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 29),
0067 GATE_VDO0_0(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 30),
0068
0069 GATE_VDO0_1(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "top_vpp", 0),
0070 GATE_VDO0_1(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "top_vpp", 1),
0071 GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 2),
0072 GATE_VDO0_1(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "top_vpp", 3),
0073 GATE_VDO0_1(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "top_vpp", 4),
0074 GATE_VDO0_1(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "top_vpp", 5),
0075 GATE_VDO0_1(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "top_vpp", 6),
0076 GATE_VDO0_1(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "top_vpp", 7),
0077 GATE_VDO0_1(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "top_vpp", 8),
0078 GATE_VDO0_1(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "top_vpp", 9),
0079 GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
0080 GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
0081 GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
0082 GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
0083 GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
0084 GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
0085
0086 GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
0087 GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
0088 GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "top_edp", 16),
0089 };
0090
0091 static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
0092 {
0093 struct device *dev = &pdev->dev;
0094 struct device_node *node = dev->parent->of_node;
0095 struct clk_hw_onecell_data *clk_data;
0096 int r;
0097
0098 clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
0099 if (!clk_data)
0100 return -ENOMEM;
0101
0102 r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
0103 if (r)
0104 goto free_vdo0_data;
0105
0106 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0107 if (r)
0108 goto unregister_gates;
0109
0110 platform_set_drvdata(pdev, clk_data);
0111
0112 return r;
0113
0114 unregister_gates:
0115 mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
0116 free_vdo0_data:
0117 mtk_free_clk_data(clk_data);
0118 return r;
0119 }
0120
0121 static int clk_mt8195_vdo0_remove(struct platform_device *pdev)
0122 {
0123 struct device *dev = &pdev->dev;
0124 struct device_node *node = dev->parent->of_node;
0125 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
0126
0127 of_clk_del_provider(node);
0128 mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
0129 mtk_free_clk_data(clk_data);
0130
0131 return 0;
0132 }
0133
0134 static struct platform_driver clk_mt8195_vdo0_drv = {
0135 .probe = clk_mt8195_vdo0_probe,
0136 .remove = clk_mt8195_vdo0_remove,
0137 .driver = {
0138 .name = "clk-mt8195-vdo0",
0139 },
0140 };
0141 builtin_platform_driver(clk_mt8195_vdo0_drv);
