clk/mediatek/clk-mt8195-topckgen.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include "clk-gate.h"
0007 #include "clk-mtk.h"
0008 #include "clk-mux.h"
0009
0010 #include <dt-bindings/clock/mt8195-clk.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 static DEFINE_SPINLOCK(mt8195_clk_lock);
0015
0016 static const struct mtk_fixed_clk top_fixed_clks[] = {
0017     FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
0018     FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 248000000),
0019     FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
0020     FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL, 533000000),
0021     FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b", NULL, 49152000),
0022     FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
0023     FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL, 166000000),
0024     FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL, 166000000),
0025     FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0, "ssusb_u3phy_p1_p_p0", NULL, 131000000),
0026     FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1", NULL, 166000000),
0027     FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
0028     FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL, 594000000),
0029 };
0030
0031 static const struct mtk_fixed_factor top_divs[] = {
0032     FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
0033     FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
0034     FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
0035     FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
0036     FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
0037     FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
0038     FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
0039     FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
0040     FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
0041     FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
0042     FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
0043     FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
0044     FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
0045     FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
0046     FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
0047     FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
0048     FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
0049     FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
0050     FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
0051     FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
0052     FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
0053     FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
0054     FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
0055     FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
0056     FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
0057     FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
0058     FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
0059     FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
0060     FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
0061     FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
0062     FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0063     FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
0064     FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
0065     FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
0066     FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
0067     FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
0068     FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
0069     FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
0070     FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
0071     FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
0072     FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
0073     FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
0074     FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
0075     FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
0076     FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
0077     FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
0078     FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
0079     FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
0080     FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
0081     FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
0082     FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
0083     FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
0084     FACTOR(CLK_TOP_HDMIRX_APLL_D3, "hdmirx_apll_d3", "hdmirx_apll", 1, 3),
0085     FACTOR(CLK_TOP_HDMIRX_APLL_D4, "hdmirx_apll_d4", "hdmirx_apll", 1, 4),
0086     FACTOR(CLK_TOP_HDMIRX_APLL_D6, "hdmirx_apll_d6", "hdmirx_apll", 1, 6),
0087     FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
0088     FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
0089     FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
0090     FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
0091     FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
0092     FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
0093     FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
0094     FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
0095     FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
0096     FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
0097     FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
0098     FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
0099     FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
0100     FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
0101     FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
0102     FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
0103     FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
0104     FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
0105     FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
0106     FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
0107     FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
0108     FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
0109     FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
0110     FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
0111     FACTOR(CLK_TOP_DGIPLL_D2, "dgipll_d2", "dgipll", 1, 2),
0112     FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
0113     FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
0114     FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc1", 1, 7),
0115     FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
0116     FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
0117     FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
0118     FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
0119     FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
0120     FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
0121 };
0122
0123 static const char * const axi_parents[] = {
0124     "clk26m",
0125     "mainpll_d4_d4",
0126     "mainpll_d7_d2",
0127     "mainpll_d4_d2",
0128     "mainpll_d5_d2",
0129     "mainpll_d6_d2",
0130     "ulposc1_d4"
0131 };
0132
0133 static const char * const spm_parents[] = {
0134     "clk26m",
0135     "ulposc1_d10",
0136     "mainpll_d7_d4",
0137     "clk32k"
0138 };
0139
0140 static const char * const scp_parents[] = {
0141     "clk26m",
0142     "univpll_d4",
0143     "mainpll_d6",
0144     "univpll_d6",
0145     "univpll_d4_d2",
0146     "mainpll_d4_d2",
0147     "mainpll_d4",
0148     "mainpll_d6_d2"
0149 };
0150
0151 static const char * const bus_aximem_parents[] = {
0152     "clk26m",
0153     "mainpll_d7_d2",
0154     "mainpll_d4_d2",
0155     "mainpll_d5_d2",
0156     "mainpll_d6"
0157 };
0158
0159 static const char * const vpp_parents[] = {
0160     "clk26m",
0161     "univpll_d6_d2",
0162     "mainpll_d5_d2",
0163     "mmpll_d6_d2",
0164     "univpll_d5_d2",
0165     "univpll_d4_d2",
0166     "mmpll_d4_d2",
0167     "mmpll_d7",
0168     "univpll_d6",
0169     "mainpll_d4",
0170     "mmpll_d5",
0171     "tvdpll1",
0172     "tvdpll2",
0173     "univpll_d4",
0174     "mmpll_d4"
0175 };
0176
0177 static const char * const ethdr_parents[] = {
0178     "clk26m",
0179     "univpll_d6_d2",
0180     "mainpll_d5_d2",
0181     "mmpll_d6_d2",
0182     "univpll_d5_d2",
0183     "univpll_d4_d2",
0184     "mmpll_d4_d2",
0185     "mmpll_d7",
0186     "univpll_d6",
0187     "mainpll_d4",
0188     "mmpll_d5_d4",
0189     "tvdpll1",
0190     "tvdpll2",
0191     "univpll_d4",
0192     "mmpll_d4"
0193 };
0194
0195 static const char * const ipe_parents[] = {
0196     "clk26m",
0197     "imgpll",
0198     "mainpll_d4",
0199     "mmpll_d6",
0200     "univpll_d6",
0201     "mainpll_d6",
0202     "mmpll_d4_d2",
0203     "univpll_d4_d2",
0204     "mainpll_d4_d2",
0205     "mmpll_d6_d2",
0206     "univpll_d5_d2"
0207 };
0208
0209 static const char * const cam_parents[] = {
0210     "clk26m",
0211     "mainpll_d4",
0212     "mmpll_d4",
0213     "univpll_d4",
0214     "univpll_d5",
0215     "univpll_d6",
0216     "mmpll_d7",
0217     "univpll_d4_d2",
0218     "mainpll_d4_d2",
0219     "imgpll"
0220 };
0221
0222 static const char * const ccu_parents[] = {
0223     "clk26m",
0224     "univpll_d6",
0225     "mainpll_d4_d2",
0226     "mainpll_d4",
0227     "univpll_d5",
0228     "mainpll_d6",
0229     "mmpll_d6",
0230     "mmpll_d7",
0231     "univpll_d4_d2",
0232     "univpll_d7"
0233 };
0234
0235 static const char * const img_parents[] = {
0236     "clk26m",
0237     "imgpll",
0238     "univpll_d4",
0239     "mainpll_d4",
0240     "univpll_d5",
0241     "mmpll_d6",
0242     "univpll_d6",
0243     "mainpll_d6",
0244     "mmpll_d4_d2",
0245     "univpll_d4_d2",
0246     "mainpll_d4_d2",
0247     "univpll_d5_d2"
0248 };
0249
0250 static const char * const camtm_parents[] = {
0251     "clk26m",
0252     "univpll_d4_d4",
0253     "univpll_d6_d2",
0254     "univpll_d6_d4"
0255 };
0256
0257 static const char * const dsp_parents[] = {
0258     "clk26m",
0259     "univpll_d6_d2",
0260     "univpll_d4_d2",
0261     "univpll_d5",
0262     "univpll_d4",
0263     "mmpll_d4",
0264     "mainpll_d3",
0265     "univpll_d3"
0266 };
0267
0268 static const char * const dsp1_parents[] = {
0269     "clk26m",
0270     "univpll_d6_d2",
0271     "mainpll_d4_d2",
0272     "univpll_d5",
0273     "mmpll_d5",
0274     "univpll_d4",
0275     "mainpll_d3",
0276     "univpll_d3"
0277 };
0278
0279 static const char * const dsp2_parents[] = {
0280     "clk26m",
0281     "univpll_d6_d2",
0282     "univpll_d4_d2",
0283     "mainpll_d4",
0284     "univpll_d4",
0285     "mmpll_d4",
0286     "mainpll_d3",
0287     "univpll_d3"
0288 };
0289
0290 static const char * const ipu_if_parents[] = {
0291     "clk26m",
0292     "univpll_d6_d2",
0293     "univpll_d5_d2",
0294     "mainpll_d4_d2",
0295     "mainpll_d6",
0296     "univpll_d5",
0297     "univpll_d4",
0298     "mmpll_d4"
0299 };
0300
0301 static const char * const mfg_parents[] = {
0302     "clk26m",
0303     "mainpll_d5_d2",
0304     "univpll_d6",
0305     "univpll_d7"
0306 };
0307
0308 static const char * const camtg_parents[] = {
0309     "clk26m",
0310     "univpll_192m_d8",
0311     "univpll_d6_d8",
0312     "univpll_192m_d4",
0313     "univpll_d6_d16",
0314     "clk26m_d2",
0315     "univpll_192m_d16",
0316     "univpll_192m_d32"
0317 };
0318
0319 static const char * const uart_parents[] = {
0320     "clk26m",
0321     "univpll_d6_d8"
0322 };
0323
0324 static const char * const spi_parents[] = {
0325     "clk26m",
0326     "mainpll_d5_d4",
0327     "mainpll_d6_d4",
0328     "msdcpll_d4",
0329     "univpll_d6_d2",
0330     "mainpll_d6_d2",
0331     "mainpll_d4_d4",
0332     "univpll_d5_d4"
0333 };
0334
0335 static const char * const spis_parents[] = {
0336     "clk26m",
0337     "univpll_d6",
0338     "mainpll_d6",
0339     "univpll_d4_d2",
0340     "univpll_d6_d2",
0341     "univpll_d4_d4",
0342     "univpll_d6_d4",
0343     "mainpll_d7_d4"
0344 };
0345
0346 static const char * const msdc50_0_h_parents[] = {
0347     "clk26m",
0348     "mainpll_d4_d2",
0349     "mainpll_d6_d2"
0350 };
0351
0352 static const char * const msdc50_0_parents[] = {
0353     "clk26m",
0354     "msdcpll",
0355     "msdcpll_d2",
0356     "univpll_d4_d4",
0357     "mainpll_d6_d2",
0358     "univpll_d4_d2"
0359 };
0360
0361 static const char * const msdc30_parents[] = {
0362     "clk26m",
0363     "univpll_d6_d2",
0364     "mainpll_d6_d2",
0365     "mainpll_d7_d2",
0366     "msdcpll_d2"
0367 };
0368
0369 static const char * const intdir_parents[] = {
0370     "clk26m",
0371     "univpll_d6",
0372     "mainpll_d4",
0373     "univpll_d4"
0374 };
0375
0376 static const char * const aud_intbus_parents[] = {
0377     "clk26m",
0378     "mainpll_d4_d4",
0379     "mainpll_d7_d4"
0380 };
0381
0382 static const char * const audio_h_parents[] = {
0383     "clk26m",
0384     "univpll_d7",
0385     "apll1",
0386     "apll2"
0387 };
0388
0389 static const char * const pwrap_ulposc_parents[] = {
0390     "ulposc1_d10",
0391     "clk26m",
0392     "ulposc1_d4",
0393     "ulposc1_d7",
0394     "ulposc1_d8",
0395     "ulposc1_d16",
0396     "mainpll_d4_d8",
0397     "univpll_d5_d8"
0398 };
0399
0400 static const char * const atb_parents[] = {
0401     "clk26m",
0402     "mainpll_d4_d2",
0403     "mainpll_d5_d2"
0404 };
0405
0406 static const char * const pwrmcu_parents[] = {
0407     "clk26m",
0408     "mainpll_d7_d2",
0409     "mainpll_d6_d2",
0410     "mainpll_d5_d2",
0411     "mainpll_d9",
0412     "mainpll_d4_d2"
0413 };
0414
0415 static const char * const dp_parents[] = {
0416     "clk26m",
0417     "tvdpll1_d2",
0418     "tvdpll2_d2",
0419     "tvdpll1_d4",
0420     "tvdpll2_d4",
0421     "tvdpll1_d8",
0422     "tvdpll2_d8",
0423     "tvdpll1_d16",
0424     "tvdpll2_d16"
0425 };
0426
0427 static const char * const disp_pwm_parents[] = {
0428     "clk26m",
0429     "univpll_d6_d4",
0430     "ulposc1_d2",
0431     "ulposc1_d4",
0432     "ulposc1_d16"
0433 };
0434
0435 static const char * const usb_parents[] = {
0436     "clk26m",
0437     "univpll_d5_d4",
0438     "univpll_d6_d4",
0439     "univpll_d5_d2"
0440 };
0441
0442 static const char * const i2c_parents[] = {
0443     "clk26m",
0444     "mainpll_d4_d8",
0445     "univpll_d5_d4"
0446 };
0447
0448 static const char * const seninf_parents[] = {
0449     "clk26m",
0450     "univpll_d4_d4",
0451     "univpll_d6_d2",
0452     "univpll_d4_d2",
0453     "univpll_d7",
0454     "univpll_d6",
0455     "mmpll_d6",
0456     "univpll_d5"
0457 };
0458
0459 static const char * const gcpu_parents[] = {
0460     "clk26m",
0461     "mainpll_d6",
0462     "univpll_d4_d2",
0463     "mmpll_d5_d2",
0464     "univpll_d5_d2"
0465 };
0466
0467 static const char * const dxcc_parents[] = {
0468     "clk26m",
0469     "mainpll_d4_d2",
0470     "mainpll_d4_d4",
0471     "mainpll_d4_d8"
0472 };
0473
0474 static const char * const dpmaif_parents[] = {
0475     "clk26m",
0476     "univpll_d4_d4",
0477     "mainpll_d6",
0478     "mainpll_d4_d2",
0479     "univpll_d4_d2"
0480 };
0481
0482 static const char * const aes_fde_parents[] = {
0483     "clk26m",
0484     "mainpll_d4_d2",
0485     "mainpll_d6",
0486     "mainpll_d4_d4",
0487     "univpll_d4_d2",
0488     "univpll_d6"
0489 };
0490
0491 static const char * const ufs_parents[] = {
0492     "clk26m",
0493     "mainpll_d4_d4",
0494     "mainpll_d4_d8",
0495     "univpll_d4_d4",
0496     "mainpll_d6_d2",
0497     "univpll_d6_d2",
0498     "msdcpll_d2"
0499 };
0500
0501 static const char * const ufs_tick1us_parents[] = {
0502     "clk26m_d52",
0503     "clk26m"
0504 };
0505
0506 static const char * const ufs_mp_sap_parents[] = {
0507     "clk26m",
0508     "msdcpll_d16"
0509 };
0510
0511 static const char * const venc_parents[] = {
0512     "clk26m",
0513     "mmpll_d4_d2",
0514     "mainpll_d6",
0515     "univpll_d4_d2",
0516     "mainpll_d4_d2",
0517     "univpll_d6",
0518     "mmpll_d6",
0519     "mainpll_d5_d2",
0520     "mainpll_d6_d2",
0521     "mmpll_d9",
0522     "univpll_d4_d4",
0523     "mainpll_d4",
0524     "univpll_d4",
0525     "univpll_d5",
0526     "univpll_d5_d2",
0527     "mainpll_d5"
0528 };
0529
0530 static const char * const vdec_parents[] = {
0531     "clk26m",
0532     "mainpll_d5_d2",
0533     "mmpll_d6_d2",
0534     "univpll_d4_d2",
0535     "mmpll_d4_d2",
0536     "mainpll_d5",
0537     "mmpll_d6",
0538     "mmpll_d5",
0539     "vdecpll",
0540     "univpll_d4",
0541     "mmpll_d4",
0542     "univpll_d6_d2",
0543     "mmpll_d9",
0544     "univpll_d6",
0545     "univpll_d5",
0546     "mainpll_d4"
0547 };
0548
0549 static const char * const pwm_parents[] = {
0550     "clk26m",
0551     "univpll_d4_d8"
0552 };
0553
0554 static const char * const mcupm_parents[] = {
0555     "clk26m",
0556     "mainpll_d6_d2",
0557     "mainpll_d7_d4",
0558 };
0559
0560 static const char * const spmi_parents[] = {
0561     "clk26m",
0562     "clk26m_d2",
0563     "ulposc1_d8",
0564     "ulposc1_d10",
0565     "ulposc1_d16",
0566     "ulposc1_d7",
0567     "clk32k",
0568     "mainpll_d7_d8",
0569     "mainpll_d6_d8",
0570     "mainpll_d5_d8"
0571 };
0572
0573 static const char * const dvfsrc_parents[] = {
0574     "clk26m",
0575     "ulposc1_d10",
0576     "univpll_d6_d8",
0577     "msdcpll_d16"
0578 };
0579
0580 static const char * const tl_parents[] = {
0581     "clk26m",
0582     "univpll_d5_d4",
0583     "mainpll_d4_d4"
0584 };
0585
0586 static const char * const dsi_occ_parents[] = {
0587     "clk26m",
0588     "mainpll_d6_d2",
0589     "univpll_d5_d2",
0590     "univpll_d4_d2"
0591 };
0592
0593 static const char * const wpe_vpp_parents[] = {
0594     "clk26m",
0595     "mainpll_d5_d2",
0596     "mmpll_d6_d2",
0597     "univpll_d5_d2",
0598     "mainpll_d4_d2",
0599     "univpll_d4_d2",
0600     "mmpll_d4_d2",
0601     "mainpll_d6",
0602     "mmpll_d7",
0603     "univpll_d6",
0604     "mainpll_d5",
0605     "univpll_d5",
0606     "mainpll_d4",
0607     "tvdpll1",
0608     "univpll_d4"
0609 };
0610
0611 static const char * const hdcp_parents[] = {
0612     "clk26m",
0613     "univpll_d4_d8",
0614     "mainpll_d5_d8",
0615     "univpll_d6_d4"
0616 };
0617
0618 static const char * const hdcp_24m_parents[] = {
0619     "clk26m",
0620     "univpll_192m_d4",
0621     "univpll_192m_d8",
0622     "univpll_d6_d8"
0623 };
0624
0625 static const char * const hd20_dacr_ref_parents[] = {
0626     "clk26m",
0627     "univpll_d4_d2",
0628     "univpll_d4_d4",
0629     "univpll_d4_d8"
0630 };
0631
0632 static const char * const hd20_hdcp_c_parents[] = {
0633     "clk26m",
0634     "msdcpll_d4",
0635     "univpll_d4_d8",
0636     "univpll_d6_d8"
0637 };
0638
0639 static const char * const hdmi_xtal_parents[] = {
0640     "clk26m",
0641     "clk26m_d2"
0642 };
0643
0644 static const char * const hdmi_apb_parents[] = {
0645     "clk26m",
0646     "univpll_d6_d4",
0647     "msdcpll_d2"
0648 };
0649
0650 static const char * const snps_eth_250m_parents[] = {
0651     "clk26m",
0652     "ethpll_d2"
0653 };
0654
0655 static const char * const snps_eth_62p4m_ptp_parents[] = {
0656     "apll2_d3",
0657     "apll1_d3",
0658     "clk26m",
0659     "ethpll_d8"
0660 };
0661
0662 static const char * const snps_eth_50m_rmii_parents[] = {
0663     "clk26m",
0664     "ethpll_d10"
0665 };
0666
0667 static const char * const dgi_out_parents[] = {
0668     "clk26m",
0669     "dgipll",
0670     "dgipll_d2",
0671     "in_dgi",
0672     "in_dgi_d2",
0673     "mmpll_d4_d4"
0674 };
0675
0676 static const char * const nna_parents[] = {
0677     "clk26m",
0678     "nnapll",
0679     "univpll_d4",
0680     "mainpll_d4",
0681     "univpll_d5",
0682     "mmpll_d6",
0683     "univpll_d6",
0684     "mainpll_d6",
0685     "mmpll_d4_d2",
0686     "univpll_d4_d2",
0687     "mainpll_d4_d2",
0688     "mmpll_d6_d2"
0689 };
0690
0691 static const char * const adsp_parents[] = {
0692     "clk26m",
0693     "clk26m_d2",
0694     "mainpll_d6",
0695     "mainpll_d5_d2",
0696     "univpll_d4_d4",
0697     "univpll_d4",
0698     "univpll_d6",
0699     "ulposc1",
0700     "adsppll",
0701     "adsppll_d2",
0702     "adsppll_d4",
0703     "adsppll_d8"
0704 };
0705
0706 static const char * const asm_parents[] = {
0707     "clk26m",
0708     "univpll_d6_d4",
0709     "univpll_d6_d2",
0710     "mainpll_d5_d2"
0711 };
0712
0713 static const char * const apll1_parents[] = {
0714     "clk26m",
0715     "apll1_d4"
0716 };
0717
0718 static const char * const apll2_parents[] = {
0719     "clk26m",
0720     "apll2_d4"
0721 };
0722
0723 static const char * const apll3_parents[] = {
0724     "clk26m",
0725     "apll3_d4"
0726 };
0727
0728 static const char * const apll4_parents[] = {
0729     "clk26m",
0730     "apll4_d4"
0731 };
0732
0733 static const char * const apll5_parents[] = {
0734     "clk26m",
0735     "apll5_d4"
0736 };
0737
0738 static const char * const i2s_parents[] = {
0739     "clk26m",
0740     "apll1",
0741     "apll2",
0742     "apll3",
0743     "apll4",
0744     "apll5",
0745     "hdmirx_apll"
0746 };
0747
0748 static const char * const a1sys_hp_parents[] = {
0749     "clk26m",
0750     "apll1_d4"
0751 };
0752
0753 static const char * const a2sys_parents[] = {
0754     "clk26m",
0755     "apll2_d4"
0756 };
0757
0758 static const char * const a3sys_parents[] = {
0759     "clk26m",
0760     "apll3_d4",
0761     "apll4_d4",
0762     "apll5_d4",
0763     "hdmirx_apll_d3",
0764     "hdmirx_apll_d4",
0765     "hdmirx_apll_d6"
0766 };
0767
0768 static const char * const spinfi_b_parents[] = {
0769     "clk26m",
0770     "univpll_d6_d8",
0771     "univpll_d5_d8",
0772     "mainpll_d4_d8",
0773     "mainpll_d7_d4",
0774     "mainpll_d6_d4",
0775     "univpll_d6_d4",
0776     "univpll_d5_d4"
0777 };
0778
0779 static const char * const nfi1x_parents[] = {
0780     "clk26m",
0781     "univpll_d5_d4",
0782     "mainpll_d7_d4",
0783     "mainpll_d6_d4",
0784     "univpll_d6_d4",
0785     "mainpll_d4_d4",
0786     "mainpll_d7_d2",
0787     "mainpll_d6_d2"
0788 };
0789
0790 static const char * const ecc_parents[] = {
0791     "clk26m",
0792     "mainpll_d4_d4",
0793     "mainpll_d5_d2",
0794     "mainpll_d4_d2",
0795     "mainpll_d6",
0796     "univpll_d6"
0797 };
0798
0799 static const char * const audio_local_bus_parents[] = {
0800     "clk26m",
0801     "clk26m_d2",
0802     "mainpll_d4_d4",
0803     "mainpll_d7_d2",
0804     "mainpll_d4_d2",
0805     "mainpll_d5_d2",
0806     "mainpll_d6_d2",
0807     "mainpll_d7",
0808     "univpll_d6",
0809     "ulposc1",
0810     "ulposc1_d4",
0811     "ulposc1_d2"
0812 };
0813
0814 static const char * const spinor_parents[] = {
0815     "clk26m",
0816     "clk26m_d2",
0817     "mainpll_d7_d8",
0818     "univpll_d6_d8"
0819 };
0820
0821 static const char * const dvio_dgi_ref_parents[] = {
0822     "clk26m",
0823     "in_dgi",
0824     "in_dgi_d2",
0825     "in_dgi_d4",
0826     "in_dgi_d6",
0827     "in_dgi_d8",
0828     "mmpll_d4_d4"
0829 };
0830
0831 static const char * const ulposc_parents[] = {
0832     "ulposc1",
0833     "ethpll_d2",
0834     "mainpll_d4_d2",
0835     "ethpll_d10"
0836 };
0837
0838 static const char * const ulposc_core_parents[] = {
0839     "ulposc2",
0840     "univpll_d7",
0841     "mainpll_d6",
0842     "ethpll_d10"
0843 };
0844
0845 static const char * const srck_parents[] = {
0846     "ulposc1_d10",
0847     "clk26m"
0848 };
0849
0850 static const char * const mfg_fast_parents[] = {
0851     "top_mfg_core_tmp",
0852     "mfgpll"
0853 };
0854
0855 static const struct mtk_mux top_mtk_muxes[] = {
0856     /*
0857      * CLK_CFG_0
0858      * top_axi and top_bus_aximem are bus clocks, should not be closed by Linux.
0859      * top_spm and top_scp are main clocks in always-on co-processor.
0860      */
0861     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi",
0862         axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL),
0863     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm",
0864         spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL),
0865     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp",
0866         scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, CLK_IS_CRITICAL),
0867     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem",
0868         bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL),
0869     /* CLK_CFG_1 */
0870     MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
0871         vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
0872     MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
0873         ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
0874     MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
0875         ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
0876     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
0877         cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
0878     /* CLK_CFG_2 */
0879     MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
0880         ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
0881     MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
0882         img_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
0883     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
0884         camtm_parents, 0x038, 0x03C, 0x040, 16, 2, 23, 0x04, 10),
0885     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
0886         dsp_parents, 0x038, 0x03C, 0x040, 24, 3, 31, 0x04, 11),
0887     /* CLK_CFG_3 */
0888     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
0889         dsp1_parents, 0x044, 0x048, 0x04C, 0, 3, 7, 0x04, 12),
0890     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
0891         dsp1_parents, 0x044, 0x048, 0x04C, 8, 3, 15, 0x04, 13),
0892     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
0893         dsp1_parents, 0x044, 0x048, 0x04C, 16, 3, 23, 0x04, 14),
0894     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
0895         dsp2_parents, 0x044, 0x048, 0x04C, 24, 3, 31, 0x04, 15),
0896     /* CLK_CFG_4 */
0897     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
0898         dsp2_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
0899     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
0900         dsp2_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
0901     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
0902         dsp_parents, 0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
0903     MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "top_ipu_if",
0904         ipu_if_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
0905     /* CLK_CFG_5 */
0906     MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
0907         mfg_parents, 0x05C, 0x060, 0x064, 0, 2, 7, 0x04, 20),
0908     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
0909         camtg_parents, 0x05C, 0x060, 0x064, 8, 3, 15, 0x04, 21),
0910     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
0911         camtg_parents, 0x05C, 0x060, 0x064, 16, 3, 23, 0x04, 22),
0912     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
0913         camtg_parents, 0x05C, 0x060, 0x064, 24, 3, 31, 0x04, 23),
0914     /* CLK_CFG_6 */
0915     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
0916         camtg_parents, 0x068, 0x06C, 0x070, 0, 3, 7, 0x04, 24),
0917     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
0918         camtg_parents, 0x068, 0x06C, 0x070, 8, 3, 15, 0x04, 25),
0919     MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
0920         uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
0921     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
0922         spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
0923     /* CLK_CFG_7 */
0924     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
0925         spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
0926     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
0927         msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29),
0928     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
0929         msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30),
0930     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
0931         msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31),
0932     /* CLK_CFG_8 */
0933     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
0934         msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0),
0935     MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
0936         intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
0937     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
0938         aud_intbus_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x08, 2),
0939     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
0940         audio_h_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 3),
0941     /*
0942      * CLK_CFG_9
0943      * top_pwrmcu is main clock in other co-processor, should not be
0944      * handled by Linux.
0945      */
0946     MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
0947         pwrap_ulposc_parents, 0x08C, 0x090, 0x094, 0, 3, 7, 0x08, 4),
0948     MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
0949         atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
0950     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",
0951         pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL),
0952     MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
0953         dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
0954     /* CLK_CFG_10 */
0955     MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
0956         dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
0957     MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
0958         dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
0959     MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
0960         disp_pwm_parents, 0x098, 0x09C, 0x0A0, 16, 3, 23, 0x08, 10),
0961     MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
0962         disp_pwm_parents, 0x098, 0x09C, 0x0A0, 24, 3, 31, 0x08, 11),
0963     /* CLK_CFG_11 */
0964     MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
0965         usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08, 12),
0966     MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
0967         usb_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2, 15, 0x08, 13),
0968     MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "top_usb_top_1p",
0969         usb_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23, 0x08, 14),
0970     MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
0971         usb_parents, 0x0A4, 0x0A8, 0x0AC, 24, 2, 31, 0x08, 15),
0972     /* CLK_CFG_12 */
0973     MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
0974         usb_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7, 0x08, 16),
0975     MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
0976         usb_parents, 0x0B0, 0x0B4, 0x0B8, 8, 2, 15, 0x08, 17),
0977     MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
0978         usb_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23, 0x08, 18),
0979     MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
0980         usb_parents, 0x0B0, 0x0B4, 0x0B8, 24, 2, 31, 0x08, 19),
0981     /* CLK_CFG_13 */
0982     MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
0983         i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08, 20),
0984     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
0985         seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15, 0x08, 21),
0986     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
0987         seninf_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23, 0x08, 22),
0988     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
0989         seninf_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31, 0x08, 23),
0990     /* CLK_CFG_14 */
0991     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
0992         seninf_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7, 0x08, 24),
0993     MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
0994         gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15, 0x08, 25),
0995     MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
0996         dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
0997     MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "top_dpmaif_main",
0998         dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31, 0x08, 27),
0999     /* CLK_CFG_15 */
1000     MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "top_aes_ufsfde",
1001         aes_fde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3, 7, 0x08, 28),
1002     MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
1003         ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15, 0x08, 29),
1004     MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US, "top_ufs_tick1us",
1005         ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1, 23, 0x08, 30),
1006     MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_CFG, "top_ufs_mp_sap_cfg",
1007         ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1, 31, 0x08, 31),
1008     /*
1009      * CLK_CFG_16
1010      * top_mcupm is main clock in other co-processor, should not be
1011      * handled by Linux.
1012      */
1013     MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1014         venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
1015     MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1016         vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
1017     MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1018         pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
1019     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm",
1020         mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, CLK_IS_CRITICAL),
1021     /*
1022      * CLK_CFG_17
1023      * top_dvfsrc is for internal DVFS usage, should not be handled by Linux.
1024      */
1025     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1026         spmi_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
1027     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1028         spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
1029     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc",
1030         dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, CLK_IS_CRITICAL),
1031     MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1032         tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
1033     /* CLK_CFG_18 */
1034     MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1, "top_tl_p1",
1035         tl_parents, 0x0F8, 0x0FC, 0x0100, 0, 2, 7, 0x0C, 8),
1036     MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1037         aes_fde_parents, 0x0F8, 0x0FC, 0x0100, 8, 3, 15, 0x0C, 9),
1038     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1039         dsi_occ_parents, 0x0F8, 0x0FC, 0x0100, 16, 2, 23, 0x0C, 10),
1040     MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1041         wpe_vpp_parents, 0x0F8, 0x0FC, 0x0100, 24, 4, 31, 0x0C, 11),
1042     /* CLK_CFG_19 */
1043     MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1044         hdcp_parents, 0x0104, 0x0108, 0x010C, 0, 2, 7, 0x0C, 12),
1045     MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1046         hdcp_24m_parents, 0x0104, 0x0108, 0x010C, 8, 2, 15, 0x0C, 13),
1047     MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_CLK, "top_hd20_dacr_ref_clk",
1048         hd20_dacr_ref_parents, 0x0104, 0x0108, 0x010C, 16, 2, 23, 0x0C, 14),
1049     MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_CCLK, "top_hd20_hdcp_cclk",
1050         hd20_hdcp_c_parents, 0x0104, 0x0108, 0x010C, 24, 2, 31, 0x0C, 15),
1051     /* CLK_CFG_20 */
1052     MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL, "top_hdmi_xtal",
1053         hdmi_xtal_parents, 0x0110, 0x0114, 0x0118, 0, 1, 7, 0x0C, 16),
1054     MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1055         hdmi_apb_parents, 0x0110, 0x0114, 0x0118, 8, 2, 15, 0x0C, 17),
1056     MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1057         snps_eth_250m_parents, 0x0110, 0x0114, 0x0118, 16, 1, 23, 0x0C, 18),
1058     MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1059         snps_eth_62p4m_ptp_parents, 0x0110, 0x0114, 0x0118, 24, 2, 31, 0x0C, 19),
1060     /* CLK_CFG_21 */
1061     MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1062         snps_eth_50m_rmii_parents, 0x011C, 0x0120, 0x0124, 0, 1, 7, 0x0C, 20),
1063     MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT, "top_dgi_out",
1064         dgi_out_parents, 0x011C, 0x0120, 0x0124, 8, 3, 15, 0x0C, 21),
1065     MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0, "top_nna0",
1066         nna_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
1067     MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
1068         nna_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
1069     /* CLK_CFG_22 */
1070     MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1071         adsp_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
1072     MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1073         asm_parents, 0x0128, 0x012C, 0x0130, 8, 2, 15, 0x0C, 25),
1074     MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M, "top_asm_m",
1075         asm_parents, 0x0128, 0x012C, 0x0130, 16, 2, 23, 0x0C, 26),
1076     MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1077         asm_parents, 0x0128, 0x012C, 0x0130, 24, 2, 31, 0x0C, 27),
1078     /* CLK_CFG_23 */
1079     MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1080         apll1_parents, 0x0134, 0x0138, 0x013C, 0, 1, 7, 0x0C, 28),
1081     MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1082         apll2_parents, 0x0134, 0x0138, 0x013C, 8, 1, 15, 0x0C, 29),
1083     MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1084         apll3_parents, 0x0134, 0x0138, 0x013C, 16, 1, 23, 0x0C, 30),
1085     MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1086         apll4_parents, 0x0134, 0x0138, 0x013C, 24, 1, 31, 0x0C, 31),
1087     /*
1088      * CLK_CFG_24
1089      * i2so4_mck is not used in MT8195.
1090      */
1091     MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1092         apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7, 0x010, 0),
1093     MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_MCK, "top_i2so1_mck",
1094         i2s_parents, 0x0140, 0x0144, 0x0148, 8, 3, 15, 0x010, 1),
1095     MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_MCK, "top_i2so2_mck",
1096         i2s_parents, 0x0140, 0x0144, 0x0148, 16, 3, 23, 0x010, 2),
1097     /*
1098      * CLK_CFG_25
1099      * i2so5_mck and i2si4_mck are not used in MT8195.
1100      */
1101     MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_MCK, "top_i2si1_mck",
1102         i2s_parents, 0x014C, 0x0150, 0x0154, 8, 3, 15, 0x010, 5),
1103     MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_MCK, "top_i2si2_mck",
1104         i2s_parents, 0x014C, 0x0150, 0x0154, 16, 3, 23, 0x010, 6),
1105     /*
1106      * CLK_CFG_26
1107      * i2si5_mck is not used in MT8195.
1108      */
1109     MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_MCK, "top_dptx_mck",
1110         i2s_parents, 0x0158, 0x015C, 0x0160, 8, 3, 15, 0x010, 9),
1111     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_CLK, "top_aud_iec_clk",
1112         i2s_parents, 0x0158, 0x015C, 0x0160, 16, 3, 23, 0x010, 10),
1113     MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1114         a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1, 31, 0x010, 11),
1115     /* CLK_CFG_27 */
1116     MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_HF, "top_a2sys_hf",
1117         a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7, 0x010, 12),
1118     MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_HF, "top_a3sys_hf",
1119         a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15, 0x010, 13),
1120     MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_HF, "top_a4sys_hf",
1121         a3sys_parents, 0x0164, 0x0168, 0x016C, 16, 3, 23, 0x010, 14),
1122     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK, "top_spinfi_bclk",
1123         spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3, 31, 0x010, 15),
1124     /* CLK_CFG_28 */
1125     MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X, "top_nfi1x",
1126         nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7, 0x010, 16),
1127     MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1128         ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15, 0x010, 17),
1129     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1130         audio_local_bus_parents, 0x0170, 0x0174, 0x0178, 16, 4, 23, 0x010, 18),
1131     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
1132         spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2, 31, 0x010, 19),
1133     /*
1134      * CLK_CFG_29
1135      * top_ulposc/top_ulposc_core/top_srck are clock source of always on co-processor,
1136      * should not be closed by Linux.
1137      */
1138     MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref",
1139         dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),
1140     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc",
1141         ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, CLK_IS_CRITICAL),
1142     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core",
1143         ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, CLK_IS_CRITICAL),
1144     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck",
1145         srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL),
1146     /*
1147      * the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled
1148      * by Linux.
1149      */
1150 };
1151
1152 static struct mtk_composite top_muxes[] = {
1153     /* CLK_MISC_CFG_3 */
1154     MUX(CLK_TOP_MFG_CK_FAST_REF, "mfg_ck_fast_ref", mfg_fast_parents, 0x0250, 8, 1),
1155 };
1156
1157 static const struct mtk_composite top_adj_divs[] = {
1158     DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
1159     DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, 0x0328, 8, 8),
1160     DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "top_i2so1_mck", 0x0320, 2, 0x0328, 8, 16),
1161     DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "top_i2so2_mck", 0x0320, 3, 0x0328, 8, 24),
1162     DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "top_aud_iec_clk", 0x0320, 4, 0x0334, 8, 0),
1163     /* apll12_div5 ~ 8 are not used in MT8195. */
1164     DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "top_dptx_mck", 0x0320, 9, 0x0338, 8, 8),
1165 };
1166
1167 static const struct mtk_gate_regs top0_cg_regs = {
1168     .set_ofs = 0x238,
1169     .clr_ofs = 0x238,
1170     .sta_ofs = 0x238,
1171 };
1172
1173 static const struct mtk_gate_regs top1_cg_regs = {
1174     .set_ofs = 0x250,
1175     .clr_ofs = 0x250,
1176     .sta_ofs = 0x250,
1177 };
1178
1179 #define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag)     \
1180     GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift,  \
1181         &mtk_clk_gate_ops_no_setclr_inv, _flag)
1182
1183 #define GATE_TOP0(_id, _name, _parent, _shift)          \
1184     GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
1185
1186 #define GATE_TOP1(_id, _name, _parent, _shift)          \
1187     GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1188
1189 static const struct mtk_gate top_clks[] = {
1190     /* TOP0 */
1191     GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "top_vpp", 0),
1192     GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "top_vpp", 1),
1193     GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "top_vpp", 2),
1194     GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "top_vpp", 3),
1195     GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses", "univpll_d2", 4),
1196     GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0", "clk26m", 5),
1197     GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1", "clk26m", 6),
1198     GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m", 9),
1199     /*
1200      * cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south
1201      * are peripheral bus clock branches.
1202      */
1203     GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east", "top_axi", 10, CLK_IS_CRITICAL),
1204     GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH, "cfg_axi_east_north", "top_axi", 11,
1205         CLK_IS_CRITICAL),
1206     GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north", "top_axi", 12, CLK_IS_CRITICAL),
1207     GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south", "top_axi", 13, CLK_IS_CRITICAL),
1208     GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test", "msdcpll_d2", 15),
1209     /* TOP1 */
1210     GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
1211     GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
1212     GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
1213     GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
1214     GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
1215     GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
1216     GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
1217     GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
1218 };
1219
1220 static const struct of_device_id of_match_clk_mt8195_topck[] = {
1221     { .compatible = "mediatek,mt8195-topckgen", },
1222     {}
1223 };
1224
1225 static int clk_mt8195_topck_probe(struct platform_device *pdev)
1226 {
1227     struct clk_hw_onecell_data *top_clk_data;
1228     struct device_node *node = pdev->dev.of_node;
1229     int r;
1230     void __iomem *base;
1231
1232     top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1233     if (!top_clk_data)
1234         return -ENOMEM;
1235
1236     base = devm_platform_ioremap_resource(pdev, 0);
1237     if (IS_ERR(base)) {
1238         r = PTR_ERR(base);
1239         goto free_top_data;
1240     }
1241
1242     r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1243                     top_clk_data);
1244     if (r)
1245         goto free_top_data;
1246
1247     r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1248     if (r)
1249         goto unregister_fixed_clks;
1250
1251     r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
1252                    &mt8195_clk_lock, top_clk_data);
1253     if (r)
1254         goto unregister_factors;
1255
1256     r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
1257                     &mt8195_clk_lock, top_clk_data);
1258     if (r)
1259         goto unregister_muxes;
1260
1261     r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
1262                     &mt8195_clk_lock, top_clk_data);
1263     if (r)
1264         goto unregister_composite_muxes;
1265
1266     r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1267     if (r)
1268         goto unregister_composite_divs;
1269
1270     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1271     if (r)
1272         goto unregister_gates;
1273
1274     platform_set_drvdata(pdev, top_clk_data);
1275
1276     return r;
1277
1278 unregister_gates:
1279     mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1280 unregister_composite_divs:
1281     mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1282 unregister_composite_muxes:
1283     mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data);
1284 unregister_muxes:
1285     mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1286 unregister_factors:
1287     mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1288 unregister_fixed_clks:
1289     mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1290 free_top_data:
1291     mtk_free_clk_data(top_clk_data);
1292     return r;
1293 }
1294
1295 static int clk_mt8195_topck_remove(struct platform_device *pdev)
1296 {
1297     struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
1298     struct device_node *node = pdev->dev.of_node;
1299
1300     of_clk_del_provider(node);
1301     mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1302     mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1303     mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data);
1304     mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1305     mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1306     mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1307     mtk_free_clk_data(top_clk_data);
1308
1309     return 0;
1310 }
1311
1312 static struct platform_driver clk_mt8195_topck_drv = {
1313     .probe = clk_mt8195_topck_probe,
1314     .remove = clk_mt8195_topck_remove,
1315     .driver = {
1316         .name = "clk-mt8195-topck",
1317         .of_match_table = of_match_clk_mt8195_topck,
1318     },
1319 };
1320 builtin_platform_driver(clk_mt8195_topck_drv);