clk/mediatek/clk-mt8195-peri_ao.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include "clk-gate.h"
0007 #include "clk-mtk.h"
0008
0009 #include <dt-bindings/clock/mt8195-clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/platform_device.h>
0012
0013 static const struct mtk_gate_regs peri_ao_cg_regs = {
0014     .set_ofs = 0x10,
0015     .clr_ofs = 0x14,
0016     .sta_ofs = 0x18,
0017 };
0018
0019 #define GATE_PERI_AO(_id, _name, _parent, _shift)           \
0020     GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0021
0022 static const struct mtk_gate peri_ao_clks[] = {
0023     GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "top_axi", 0),
0024     GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "top_axi", 1),
0025     GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "top_axi", 3),
0026     GATE_PERI_AO(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "top_spinor", 5),
0027     GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_BUS, "peri_ao_ssusb_1p_bus", "top_usb_top_1p", 7),
0028     GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_XHCI, "peri_ao_ssusb_1p_xhci", "top_ssusb_xhci_1p", 8),
0029     GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "top_usb_top_2p", 9),
0030     GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "top_ssusb_xhci_2p", 10),
0031     GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "top_usb_top_3p", 11),
0032     GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "top_ssusb_xhci_3p", 12),
0033     GATE_PERI_AO(CLK_PERI_AO_SPINFI, "peri_ao_spinfi", "top_spinfi_bclk", 15),
0034     GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac", "top_snps_eth_250m", 16),
0035     GATE_PERI_AO(CLK_PERI_AO_NFI_H, "peri_ao_nfi_h", "top_axi", 19),
0036     GATE_PERI_AO(CLK_PERI_AO_FNFI1X, "peri_ao_fnfi1x", "top_nfi1x", 20),
0037     GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_MEM, "peri_ao_pcie_p0_mem", "mem_466m", 24),
0038     GATE_PERI_AO(CLK_PERI_AO_PCIE_P1_MEM, "peri_ao_pcie_p1_mem", "mem_466m", 25),
0039 };
0040
0041 static const struct mtk_clk_desc peri_ao_desc = {
0042     .clks = peri_ao_clks,
0043     .num_clks = ARRAY_SIZE(peri_ao_clks),
0044 };
0045
0046 static const struct of_device_id of_match_clk_mt8195_peri_ao[] = {
0047     {
0048         .compatible = "mediatek,mt8195-pericfg_ao",
0049         .data = &peri_ao_desc,
0050     }, {
0051         /* sentinel */
0052     }
0053 };
0054
0055 static struct platform_driver clk_mt8195_peri_ao_drv = {
0056     .probe = mtk_clk_simple_probe,
0057     .remove = mtk_clk_simple_remove,
0058     .driver = {
0059         .name = "clk-mt8195-peri_ao",
0060         .of_match_table = of_match_clk_mt8195_peri_ao,
0061     },
0062 };
0063 builtin_platform_driver(clk_mt8195_peri_ao_drv);