clk/mediatek/clk-mt8195-infra_ao.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include "clk-gate.h"
0007 #include "clk-mtk.h"
0008
0009 #include <dt-bindings/clock/mt8195-clk.h>
0010 #include <dt-bindings/reset/mt8195-resets.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/platform_device.h>
0013
0014 static const struct mtk_gate_regs infra_ao0_cg_regs = {
0015     .set_ofs = 0x80,
0016     .clr_ofs = 0x84,
0017     .sta_ofs = 0x90,
0018 };
0019
0020 static const struct mtk_gate_regs infra_ao1_cg_regs = {
0021     .set_ofs = 0x88,
0022     .clr_ofs = 0x8c,
0023     .sta_ofs = 0x94,
0024 };
0025
0026 static const struct mtk_gate_regs infra_ao2_cg_regs = {
0027     .set_ofs = 0xa4,
0028     .clr_ofs = 0xa8,
0029     .sta_ofs = 0xac,
0030 };
0031
0032 static const struct mtk_gate_regs infra_ao3_cg_regs = {
0033     .set_ofs = 0xc0,
0034     .clr_ofs = 0xc4,
0035     .sta_ofs = 0xc8,
0036 };
0037
0038 static const struct mtk_gate_regs infra_ao4_cg_regs = {
0039     .set_ofs = 0xe0,
0040     .clr_ofs = 0xe4,
0041     .sta_ofs = 0xe8,
0042 };
0043
0044 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag)                \
0045     GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
0046         &mtk_clk_gate_ops_setclr, _flag)
0047
0048 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
0049     GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
0050
0051 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag)        \
0052     GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
0053         &mtk_clk_gate_ops_setclr, _flag)
0054
0055 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
0056     GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
0057
0058 #define GATE_INFRA_AO2(_id, _name, _parent, _shift)         \
0059     GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0060
0061 #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag)        \
0062     GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
0063         &mtk_clk_gate_ops_setclr, _flag)
0064
0065 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
0066     GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
0067
0068 #define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag)        \
0069     GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
0070         &mtk_clk_gate_ops_setclr, _flag)
0071
0072 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \
0073     GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
0074
0075 static const struct mtk_gate infra_ao_clks[] = {
0076     /* INFRA_AO0 */
0077     GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
0078     GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
0079     GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
0080     GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
0081     /* infra_ao_sej is main clock is for secure engine with JTAG support */
0082     GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
0083     GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
0084     GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8),
0085     GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9),
0086     GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
0087     GATE_INFRA_AO0(CLK_INFRA_AO_PWM_H, "infra_ao_pwm_h", "top_axi", 15),
0088     GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
0089     GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
0090     GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
0091     GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
0092     GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
0093     GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
0094     GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
0095     GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
0096     GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25),
0097     GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26),
0098     GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
0099     GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28),
0100     GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
0101     /* INFRA_AO1 */
0102     GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
0103     GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
0104     GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc50_0_hclk", 2),
0105     GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
0106     GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, "infra_ao_cg1_msdc2", "top_axi", 5),
0107     GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_src", "top_msdc50_0", 6),
0108     GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
0109     GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
0110     GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
0111     GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12),
0112     GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, "infra_ao_cec_66m_h", "top_axi", 13),
0113     GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, "infra_ao_irrx", "top_axi", 14),
0114     GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15),
0115     GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_src", "top_msdc30_1", 16),
0116     GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, "infra_ao_cec_66m_b", "top_axi", 17),
0117     GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18),
0118     /* infra_ao_device_apc is for device access permission control module */
0119     GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_device_apc", "top_axi", 20,
0120                  CLK_IS_CRITICAL),
0121     GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, "infra_ao_ecc_66m_h", "top_axi", 23),
0122     GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24),
0123     GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
0124     GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26),
0125     GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29),
0126     GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc_f26m", "clk26m", 31),
0127     /* INFRA_AO2 */
0128     GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0),
0129     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, "infra_ao_ssusb", "top_usb_top", 1),
0130     GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2),
0131     GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, "infra_ao_cldma_b", "top_axi", 3),
0132     GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_B, "infra_ao_audio_26m_b", "clk26m", 4),
0133     GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
0134     GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
0135     GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
0136     GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, "infra_ao_unipro_sys", "top_ufs", 11),
0137     GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, "infra_ao_unipro_tick", "top_ufs_tick1us", 12),
0138     GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, "infra_ao_ufs_mp_sap_b", "top_ufs_mp_sap_cfg", 13),
0139     GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "top_pwrmcu", 15),
0140     GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "top_axi", 17),
0141     GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, "infra_ao_apdma_b", "top_axi", 18),
0142     GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
0143     GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
0144     GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
0145     GATE_INFRA_AO2(CLK_INFRA_AO_AES_UFSFDE, "infra_ao_aes_ufsfde", "top_ufs", 28),
0146     GATE_INFRA_AO2(CLK_INFRA_AO_AES, "infra_ao_aes", "top_aes_ufsfde", 29),
0147     GATE_INFRA_AO2(CLK_INFRA_AO_UFS_TICK, "infra_ao_ufs_tick", "top_ufs_tick1us", 30),
0148     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_XHCI, "infra_ao_ssusb_xhci", "top_ssusb_xhci", 31),
0149     /* INFRA_AO3 */
0150     GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0f", "top_msdc50_0", 0),
0151     GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1f", "top_msdc50_0", 1),
0152     GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2f", "top_msdc50_0", 2),
0153     GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5),
0154     GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7),
0155     GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8),
0156     GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, "infra_ao_cg3_msdc2", "top_msdc30_2", 9),
0157     GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10),
0158     GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15),
0159     GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, "infra_ao_gcpu_66m_b", "top_axi", 16),
0160     GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, "infra_ao_gcpu_133m_b", "top_axi", 17),
0161     GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20),
0162     GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24),
0163     /* infra_ao_device_apc_sync is for device access permission control module */
0164     GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_device_apc_sync", "top_axi", 25,
0165                  CLK_IS_CRITICAL),
0166     GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26),
0167     GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, "infra_ao_spis0", "top_spis", 28),
0168     GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, "infra_ao_spis1", "top_spis", 29),
0169     /* INFRA_AO4 */
0170     /* infra_ao_133m_m_peri infra_ao_66m_m_peri are main clocks of peripheral */
0171     GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_M_PERI, "infra_ao_133m_m_peri", "top_axi", 0,
0172                  CLK_IS_CRITICAL),
0173     GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_M_PERI, "infra_ao_66m_m_peri", "top_axi", 1,
0174                  CLK_IS_CRITICAL),
0175     GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", "pextp_pipe", 7),
0176     GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P1, "infra_ao_pcie_pl_p_250m_p1",
0177                "ssusb_u3phy_p1_p_p0", 8),
0178     GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_P1_TL_96M, "infra_ao_pcie_p1_tl_96m", "top_tl_p1", 17),
0179     GATE_INFRA_AO4(CLK_INFRA_AO_AES_MSDCFDE_0P, "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
0180     GATE_INFRA_AO4(CLK_INFRA_AO_UFS_TX_SYMBOL, "infra_ao_ufs_tx_symbol", "ufs_tx_symbol", 22),
0181     GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL, "infra_ao_ufs_rx_symbol", "ufs_rx_symbol", 23),
0182     GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL1, "infra_ao_ufs_rx_symbol1", "ufs_rx_symbol1", 24),
0183     GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
0184 };
0185
0186 static u16 infra_ao_rst_ofs[] = {
0187     INFRA_RST0_SET_OFFSET,
0188     INFRA_RST1_SET_OFFSET,
0189     INFRA_RST2_SET_OFFSET,
0190     INFRA_RST3_SET_OFFSET,
0191     INFRA_RST4_SET_OFFSET,
0192 };
0193
0194 static u16 infra_ao_idx_map[] = {
0195     [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
0196     [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
0197     [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
0198 };
0199
0200 static struct mtk_clk_rst_desc infra_ao_rst_desc = {
0201     .version = MTK_RST_SET_CLR,
0202     .rst_bank_ofs = infra_ao_rst_ofs,
0203     .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
0204     .rst_idx_map = infra_ao_idx_map,
0205     .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
0206 };
0207
0208 static const struct mtk_clk_desc infra_ao_desc = {
0209     .clks = infra_ao_clks,
0210     .num_clks = ARRAY_SIZE(infra_ao_clks),
0211     .rst_desc = &infra_ao_rst_desc,
0212 };
0213
0214 static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
0215     {
0216         .compatible = "mediatek,mt8195-infracfg_ao",
0217         .data = &infra_ao_desc,
0218     }, {
0219         /* sentinel */
0220     }
0221 };
0222
0223 static struct platform_driver clk_mt8195_infra_ao_drv = {
0224     .probe = mtk_clk_simple_probe,
0225     .remove = mtk_clk_simple_remove,
0226     .driver = {
0227         .name = "clk-mt8195-infra_ao",
0228         .of_match_table = of_match_clk_mt8195_infra_ao,
0229     },
0230 };
0231 builtin_platform_driver(clk_mt8195_infra_ao_drv);